Task-accurate performance modeling in SystemC for real-time multi-processor architectures

Streubühr, Martin; Falk, Joachim; Haubelt, Ch.; Teich, Jürgen; Dorsch, Rainer G.; Schlipf, T.

doi:10.1109/date.2006.243832

Cited by 12 publications

(11 citation statements)

References 1 publication

(2 reference statements)

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“…The corresponding VHDL model consists of approximately 18k SLOC. In contrast to the InfiniBand HLM which has been modeled using only the basic model [2], we did not encounter any deadlocks during the verification of the Parallel Sysplex HLM in the hardware verification environment.…”

Section: B Resultsmentioning

confidence: 81%

“…With only the basic model available, a high-level model for complex network protocol engines could be derived in principle, as we already showed in [2] by modeling and simulating an InfiniBand Host Channel Adapter (HCA).…”

Section: High-level Design Methodologymentioning

confidence: 99%

“…For architectural exploration, the HLM is typically augmented with architecture information, i.e., number and type of processing and communication resources including buses and memories. By specifying the HLM mapping to this architecture, and by using estimates for execution times, so called Virtual Architecture Models can be generated, permitting a combined functional and timed simulation, and hence, an early performance estimation [2], [3]. After selecting the platform (i.e., an architecture instance) for implementation, the HLM can be reused in various scenarios: In hardware design, the HLM serves as golden model; in software design, parts of the executable HLM are integrated into a virtual prototype, allowing software development to start without the need for a hardware prototype.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Efficient High-Level modeling in the networking domain

Zebelein¹,

Falk²,

Haubelt³

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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-Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainably improve productivity. However, writing good HLMs for complex systems is still a challenging task. In the context of network controller design, modeling complexity has two major sources: (1) the functionality to handle a single connection, and (2) the number of connections to be handled in parallel. In this paper, we will propose an efficient actor-oriented modeling approach for complex systems by (1) integrating hierarchical FSMs into dynamic dataflow models, and (2) providing new channel types to allow concurrent processing of multiple connections. We will show the applicability of our proposed modeling approach to real-world system designs by presenting results from modeling and simulating a network controller for the Parallel Sysplex architecture used in IBM System z mainframes.

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Section: B Resultsmentioning

confidence: 81%

Section: High-level Design Methodologymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Efficient High-Level modeling in the networking domain

Zebelein¹,

Falk²,

Haubelt³

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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show abstract

“…Several approaches based on abstract task graphs [9,10,12,15] have been proposed as well. In this case, a pure functional SystemC model is mapped onto an architecture model including an abstract RTOS.…”

Section: Related Workmentioning

confidence: 99%

A program state machine based virtual processing model in SystemC

et al. 2015

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The Program State Machine (PSM) Model of Computation offers a rich set of modeling elements to describe behavioral and structural hierarchy, concurrency, synchronization, state transitions and timing. With the rising software complexity of today's embedded systems, the use of Real-Time Operating Systems (RTOS) has become state-of-the-art for nearly all System-on-Chip designs. Regrettably, the PSM model itself has insufficient support for the specification of the preemptive dynamic scheduling behavior of an RTOS. In this paper, we propose a model for dynamically dispatching PSM models on a virtual processing element. Our model aims to abstract from the targeted RTOS and the processor core through execution time annotations and a flexible preemptive scheduler model. Mapping a PSM model to a set of scheduled virtual processing elements only requires minor model transformation and enables early exploration of different processing element mappings and scheduling policies. Our virtual processing model for PSMs is realized on top of the SystemC library. We evaluate the proposed virtual processing model using a Canny edge detection filter.

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“…The objectives of the optimization are throughput in terms of frames per second (fps), latency in terms of milliseconds, and chip area in terms of the number of gates. The performance evaluation of each candidate implementation is carried out by a fast high-level simulation that dynamically annotates the performance characteristics from a selected allocation to the application [16]. The chip area is approximated by a linear cost function.…”

Section: Case Studymentioning

confidence: 99%

Combined system synthesis and communication architecture exploration for MPSoCs

Lukasiewycz

Streubühr

Glaß

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

Self Cite

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In this paper, a novel design space exploration approach is proposed that enables a concurrent optimization of the topology, the process binding, and the communication routing of a system. Given an application model written in SystemC TLM 2.0, the proposed approach performs a fully automatic optimization by a simultaneous resource allocation, task binding, data mapping, and transaction routing for MPSoC platforms. To cope with the huge complexity of the design space, a transformation of the transaction level model to a graph-based model and symbolic representation that allows multi-objective optimization is presented. Results from optimizing a Motion-JPEG decoder illustrate the effectiveness of the proposed approach.

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Task-accurate performance modeling in SystemC for real-time multi-processor architectures

Abstract: We propose a novel framework, called Virtual Processing Components (VPC), that permits the modeling and simulation of multiple processors running arbitrary scheduling strategies in SystemC. The granularity is given by task accuracy that guarantees a small simulation overhead.

Cited by 12 publications

References 1 publication

Efficient High-Level modeling in the networking domain

Efficient High-Level modeling in the networking domain

A program state machine based virtual processing model in SystemC

Combined system synthesis and communication architecture exploration for MPSoCs

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