Targeting FPGA DSP Slices for a Large Integer Multiplier for Integer Based FHE

Abstract

Abstract. Homomorphic encryption offers potential for secure cloud computing. However due to the complexity of homomorphic encryption schemes, performance of implemented schemes to date have been unpractical. This work investigates the use of hardware, specifically Field Programmable Gate Array (FPGA) technology, for implementing the building blocks involved in somewhat and fully homomorphic encryption schemes in order to assess the practicality of such schemes. We concentrate on the selection of a suitable multiplication algorithm and hardware architecture for large integer multiplication, one of the main bottlenecks in many homomorphic encryption schemes. We focus on the encryption step of an integer-based fully homomorphic encryption (FHE) scheme. We target the DSP48E1 slices available on Xilinx Virtex 7 FPGAs to ascertain whether the large integer multiplier within the encryption step of a FHE scheme could fit on a single FPGA device. We find that, for toy size parameters for the FHE encryption step, the large integer multiplier fits comfortably within the DSP48E1 slices, greatly improving the practicality of the encryption step compared to a software implementation. As multiplication is an important operation in other FHE schemes, a hardware implementation using this multiplier could also be used to improve performance of these schemes.

Evaluation of Large Integer Multiplication Methods on Hardware

“…A multiplication of two n-word numbers produces 2n − 1 partial products, given any word of arbitrary bit length. Figure 1 outlines the proposed hardware architecture of the Comba multiplier in this research targeting the Xilinx Virtex-7 platform and in particular the available DSP slices, as previously proposed for use in the design of an encryption step for FHE schemes [16], [47]. The abundant Xilinx DSP48E1 slices available on Virtex-7 FPGAs are specifically optimised for DSP operations.…”

“…1. Comba multiplier architecture [16], [47] 16-bit multiplication input is chosen to ensure efficient computation on the FPGA platform. These blocks are shifted in opposing directions and input into the multiply-accumulate (MAC) blocks in the DSP slices.…”

An Application of Partial Homomorphic Encryption in Computer System with Limited Resources

“…If this property is used in cloud computing, it can solve some of security issues. This is the main reason why academic society is interested in a usage of homomorphic cryptosystems in the cloud [8][9][10][11].…”

Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption

“…This integer-based scheme has been extended by Coron et al to minimise public-key sizes [9], this extension is referred to in this work as an abbreviation of the authors' names, CNT. Previous research by the authors [21]- [23] has investigated the acceleration of the large integer multiplication required in this FHE scheme. The possibility of implementing the multiplications required in the integer-based FHE scheme using the embedded DSP blocks on a Xilinx Virtex-7 FPGA with the Comba multiplication algorithm was analysed by Moore et al [21], [22].…”

“…Previous research by the authors [21]- [23] has investigated the acceleration of the large integer multiplication required in this FHE scheme. The possibility of implementing the multiplications required in the integer-based FHE scheme using the embedded DSP blocks on a Xilinx Virtex-7 FPGA with the Comba multiplication algorithm was analysed by Moore et al [21], [22]. Also, Cao et al [23] presented the first hardware implementation of the encryption step in the CNT FHE scheme, with a significant speed-up of 54.42 compared with the corresponding software reference implementation [9].…”