2023
DOI: 10.48550/arxiv.2301.10032
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Taming Large Bounds in Synthesis from Bounded-Liveness Specifications (Full Version)

Abstract: Automatic synthesis from temporal logic specifications is an attractive alternative to manual system design, due to its ability to generate correct-by-construction implementations from high-level specifications. Due to the high complexity of the synthesis problem, significant research efforts have been directed at developing practically efficient approaches for restricted specification language fragments. In this paper we focus on the Safety LTL fragment of Linear Temporal Logic (LTL) syntactically extended wi… Show more

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Cited by 1 publication
(4 citation statements)
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“…All times are wall-clock times. A detailed description of the benchmarks is given in the full version [13].…”
Section: Discussionmentioning
confidence: 99%
See 3 more Smart Citations
“…All times are wall-clock times. A detailed description of the benchmarks is given in the full version [13].…”
Section: Discussionmentioning
confidence: 99%
“…We note, however, that in the worst case it is not possible to avoid this blowup. This is stated in the next theorem, the proof of which is given in the full version [13].…”
Section: Solving Countdown-timer Gamesmentioning
confidence: 90%
See 2 more Smart Citations