TAM Design and Optimization for Transparency-Based SoC Test

This paper presents a wrapper and TAM co-optimization method for reuse of SoC functional interconnects to minimize test time under area constraint. The proposed method consists of (1) an ILP formulation for wrapper and transparent TAM cooptimization, and (2) a simulated annealing based heuristic approach to reduce the computational cost of the proposed ILP model. Experimental results show the effectiveness of the proposed methods compared to the previous transparency-based TAM approaches and the conventional dedicated test bus approaches. keywords: SoC test, wrapper, TAM, reuse of interconnect.

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Wrapper and TAM co-optimization for reuse of SoC functional interconnects

Yoneda

Fujiwara

2008

Proceedings of the Conference on Design, Automation and Test in Europe

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TAM Design and Optimization for Transparency-Based SoC Test

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References 16 publications

Wrapper and TAM co-optimization for reuse of SoC functional interconnects

Wrapper and TAM co-optimization for reuse of SoC functional interconnects

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