Systolic Architecture for Adaptive Censoring CFAR PI Detector

Abstract

A new parallel algorithm for signal processing and a parallel systolic architecture of a robust constant false alarm rate (CFAR) processor with post-detection integration and adaptive censoring (RACPI) is presented in the paper. This detector is effective in conditions of flow from strong impulse interference. The ACPI CFAR processor uses sorting and censoring algorithms. We offer the sorting algorithm to be realized on the basis of the odd-even transposition sort method. We propose the censoring algorithm to be used for obtaining of the noise level estimation and for estimation of the impulse interference parameters. These parameters are needed for automatically choosing the scale factor, which keeps the false alarm rate constant. The real-time implementation of this detection algorithm requires large computational resources because of the great volume and high speed of the incoming data. The time consumption of the sorting and censoring procedures is also very high and therefore the practical realization is difficult. For all these reasons, we choose systolic architectures in the considered case for being more effective than conventional multiprocessor architectures. The computational losses of the systolic architecture are estimated in terms of the number of the processor elements, the computational time and the speed-up needed for realtime implementation.