SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications

Abstract

and MICHAEL MEREDITH Forte Design SystemsWith increasing design complexity, the gap from ESL (Electronic System Level) design to RTL synthesis becomes more and more crucial to many industrial projects. Although several behavioral synthesis tools exist to automatically generate synthesizable RTL code from C/C++/SystemCbased input descriptions and software generation for embedded processors is automated as well, an efficient ESL synthesis methodology combining both is still missing. This article presents SYS-TEMCODESIGNER, a novel SystemC-based ESL tool to automatically optimize a hardware/software SoC (System on Chip) implementation with respect to several objectives. Starting from a SystemC behavioral model, SYSTEMCODESIGNER automatically extracts the mathematical model, performs a behavioral synthesis step, and explores the multiobjective design space using state-of-the-art multiobjective optimization algorithms. During design space exploration, a single design point is evaluated by simulating highly accurate performance models, which are automatically generated from the SystemC behavioral model and the behavioral synthesis results. Moreover, SYSTEMCODESIGNER permits the automatic generation of bit streams for FPGA targets from any previously optimized SoC implementation. Thus SYSTEMCODESIGNER is the first fully automated ESL synthesis tool providing a correct-by-construction generation of hardware/software SoC implementations. As a case study, a model of a Motion-JPEG decoder was automatically optimized and implemented using SYSTEMCODESIGNER. Several synthesized SoC variants based on this model show different tradeoffs between required hardware costs and achieved system throughput, ranging from software-only solutions to pure hardware implementations that reach real-time performance for QCIF streams on a 50MHz FPGA. ACM Reference Format:Keinert, J., Streubühr, M., Schlichter, T., Falk, J., Gladigau, J., Haubelt, C., and Teich, J. 2009. SYSTEMCODESIGNER-An automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming application.

TECSCE: HW/SW Codesign Framework for Data Parallelism Based on Software Component

“…SystemCoDesigner [12] supports a fast design space exploration and rapid prototyping of behavioral SystemC models by using an actor-oriented approach.…”

Synthesis of Custom Hardware from ADA with Artificial Intelligence Techniques

“…In [17] an actor, that is used to model every module or system process, communicates with other actors via communication channels. These actors are used by the System Co-Designer [17] to exercise electronic system level (ESL) design space exploration.…”

“…These actors are used by the System Co-Designer [17] to exercise electronic system level (ESL) design space exploration. In [18] the SURYA system utilises the Simplify theorem prover to prove that the RTL model generated by HLS tools is functionally-equivalent to the specification.…”

A system-level synthesis approach from formal application models to generic bus-based MPSoCs

“…For this purpose, we introduce well defined intermediate transaction level models as the canonical interface between various formal models and generic implementations. As a proof of concept, we couple representatives from both classes, namely the SystemCoDesigner [7] and the System-On-Chip Environment (SCE) [8] solutions. We concentrate on bus-based MPSoCs, as these architectures are most common, and memory-mapped bus modeling is the focus of the TLM 2.0 standard [9].…”

“…PeaCE [14], on the other hand, supports automatic computation refinement while decision making mostly has to be performed manually. Daedalus [15], Koski [16], and SystemCoDesigner (SCD) [7] are system-level synthesis tools that automatically map applications to MPSoC targets. These tools support decision making and refinement for application computation, but decision making and refinement for communication is only supported for limited types of communication architectures.…”