SystemC Implementation of a NoC

Portero, Antoni; Pla, R.; Carrabina, Jordi

doi:10.1109/icit.2005.1600805

Cited by 14 publications

(10 citation statements)

References 6 publications

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“…SystemCbased NoC simulators [97][98][99][100][101][102][103] are powerful tools to evaluate different NoC configurations by means of simulation. Xpipes [103] is an example of this type.…”

Section: Network On Chip Thermal and Energy Aspectsmentioning

confidence: 99%

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Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Zarrin

Aguiar

Barraca

2017

Simulation Modelling Practice and Theory

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This is the accepted version of the paper.This version of the publication may differ from the final published version. Permanent repository link AbstractThe architecture design of peta-scale computing systems is complex and presents lots of difficulties to designs, as current tools lack support for relevant features of future scenarios. Novel systems must be designed with great care and tools, such as manycore architecture simulators, must be adapted accordingly. However, current simulation tools are very slow, often specific-purposeoriented, suffer from various issues and are rarely able to simulate thousands of cores. The emergence of peta-scale systems and the upcoming manycore era brings nevertheless new challenges to computing systems and architectures, adding further difficulties and requirements on the development of the corresponding simulators. Furthermore, the design of architecture simulators for manycore systems involve methods and techniques from various interdisciplinary research areas, which in turn brings more challenges in different aspects. As system complexity grows, the growth of the simulation capacity is being outpaced (reaching the so called simulation wall). In this paper, we present the challenges for simulating future large scale manycore environments, and we investigate the adequacy of current modeling and simulation tools, methodologies and techniques. The aim of this work is to highlight how current approaches can best deal with the identified problems, smoothing the challenges of research in future peta-scale systems.

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“…SystemCbased NoC simulators [97][98][99][100][101][102][103] are powerful tools to evaluate different NoC configurations by means of simulation. Xpipes [103] is an example of this type.…”

Section: Network On Chip Thermal and Energy Aspectsmentioning

confidence: 99%

“…In the current literature, SystemC has also been extensively used for designing NoC simulators, due to the powerful capa- [97][98][99][100][101][102][103]. SystemC based simulators are accurate and sufficient for validating hardware specifications.…”

Section: Systemcmentioning

confidence: 99%

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Zarrin

Aguiar

Barraca

2017

Simulation Modelling Practice and Theory

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“…SCENIC is used to create, simulate, and explore the proposed CGRA system in Section III. SystemC has been used in many academic and industrial research projects, mainly for exploring complex architectures such as Network-on-Chip (NoC) [7] or multi-processor systems [8]. The advantages with SystemC include modeling at different abstraction levels, simplified hardware/software co-simulation, and high simulation speed.…”

Section: Modeling and Exploration Using Scenicmentioning

confidence: 99%

Modeling and exploration of a reconfigurable architecture for digital holographic imaging

Lenart

Svensson

Öwall

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-The use of coarse-grain reconfigurable architectures (CGRA) is a suitable alternative for hardware acceleration in many application areas, including digital holographic imaging. In this paper, we propose a CGRA-based system with an array of processing and memory cells, which communicate using a local and a global communication network, and a stream memory controller to manage data transfers to external memory. We present our SystemC-based exploration environment (SCENIC) and methodology used to construct and evaluate systems containing reconfigurable architectures. A case study illustrates the advantages with rapid system level exploration to find and solve bottlenecks in complex designs prior to RTL description.

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“…Over the past years, SystemC has gained more interest in both academia and industry due to the capability of co-simulating software and hardware and a simple way of refining abstract models down to clock cycle accurate hardware. Simulation frameworks and NoC models based on SystemC has been presented in [11] and [8], but focusing mainly on communication. In contrast, we are currently developing a simulation and exploration tool based on the Open SystemC Initiative (OSCI) SystemC library to build, configure, and explore NoC architectures.…”

Section: Related Workmentioning

confidence: 99%

A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing

Lenart

Svensson

Öwall

2008

4th IEEE International Symposium on Electronic Design, Test and Applications (Delta 2008)

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This paper presents a hybrid interconnect network consisting of a local network with dedicated wires and a global hierarchical network. A distributed memory approach enables the possibility to use generic memory banks as routing buffers, simplifies the implementation and reduces the area requirements of routers. A SystemC simulation environment (SCENIC) has been developed to simulate and instrument models, and to setup different topologies and scenarios. Modules are designed as transaction level models to improve design time and simulation speed.

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SystemC Implementation of a NoC

Cited by 14 publications

References 6 publications

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Modeling and exploration of a reconfigurable architecture for digital holographic imaging

A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing

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