SystemC-defined SIMD instructions for a CMP/SMT ASIC platform

Chouliaras, V.A.; Koutsomyti, K.; Jacobs, T.R.; Parr, S.; Mulvaney, David; Thomson, R. B.

doi:10.1109/norchp.2006.329228

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Custom Core (Ccore) and Peripheral Wrapper1

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2016

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“…These peripherals are typically stream accelerators, designed with ESL flows [28] or directly in RTL, and access the common system memory via pipelined ports. Fig.…”

Section: Custom Core (Ccore) and Peripheral Wrappermentioning

confidence: 99%

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

Chouliaras

Stevens

Dwyer

2016

Microprocessors and Microsystems

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performance increase on synthetic benchmarks, x5 on a parallel Mandelbrot implementation, 66% better on a threaded JPEG implementation, 79% better on an edge-detection benchmark and~13% improvement on DES compared to the Leon3MP CMP. In the range of 2 to 8 cores VThreads demonstrates a post-route (statistical) power reduction between 65% to 57% at an area increase of 1.2%-10% for 1-8 cores, compared to a similarly-configured Leon3MP CMP. This combination of micro-architectural features, scalability, extensibility, hardware support for low-latency PThreads, power efficiency and area make the processor an attractive proposition for low-power, deeply-embedded applications requiring minimum OS support.

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“…These peripherals are typically stream accelerators, designed with ESL flows [28] or directly in RTL, and access the common system memory via pipelined ports. Fig.…”

Section: Custom Core (Ccore) and Peripheral Wrappermentioning

confidence: 99%