Systematic software-based self-test for pipelined processors

Psarakis, Mihalis; Gizopoulos, Dimitris; Hatzimihail, M.; Paschalis, A.; Raghunathan, Anand; Ravi, S.

doi:10.1145/1146909.1147014

Cited by 34 publications

(11 citation statements)

References 24 publications

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“…Processor down time for these testing mechanisms can be extremely high, a few seconds at a time for the solution proposed in [9]. Software-based techniques utilize software routines providing high fault coverage with no hardware additions [1,14]. Their focus is to achieve an elevated fault coverage across all structures of the CPU, posing a significant performance overhead, regardless of the dynamic usage and health of the processor.…”

Section: Related Workmentioning

confidence: 99%

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Application-Aware diagnosis of runtime hardware faults

Pellegrini¹,

Bertacco²

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Extreme technology scaling in silicon devices drastically affects reliability, particularly because of runtime failures induced by transistor wearout. Current online testing mechanisms focus on testing all components in a microprocessor, including hardware that has not been exercised, and thus have high performance penalties.We propose a hybrid hardware/software online testing solution where components that are heavily utilized by the software application are tested more thoroughly and frequently. Thus, our online testing approach focuses on the processor units that affect application correctness the most, and it achieves high coverage while incurring minimal performance overhead. We also introduce a new metric, Application-Aware Fault Coverage, measuring a test's capability to detect faults that might have corrupted the state or the output of an application. Test coverage is further improved through the insertion of observation points that augment the coverage of the testing system. By evaluating our technique on a Sun OpenSPARC T1, we show that our solution maintains high Application-Aware Fault Coverage while reducing the performance overhead of online testing by more than a factor of 2 when compared to solutions oblivious to application's behavior. Specifically, we found that our solution can achieve 95% fault coverage while maintaining a minimal performance overhead (1.3%) and area impact (0.4%).

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Section: Related Workmentioning

confidence: 99%

“…In the hardware testing community, it is recognized that softwarebased fault testing can be a very effective way to expose the majority of faults in a processor design [14]. Several techniques has been proposed in the literature to build software test routines to this end [3].…”

Section: Software Testsmentioning

confidence: 99%

Application-Aware diagnosis of runtime hardware faults

Pellegrini¹,

Bertacco²

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…There is a rich literature in this field, covering various aspects. For example, software-based selftesting techniques for processor cores have been extensively studied [21], [22]. Design-specific solutions have also been explored, see [23] for UltraSPARC T1 microprocessor and [24] for ARM CORTEX-A8.…”

Section: Online Testingmentioning

confidence: 99%

Economic Analysis of Testing Homogeneous Manycore Chips

Huang

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The employment of a large number of structurally identical cores on a single silicon die is generally regarded as a promising solution for tera-scale computation, known as manycore chips. To ensure the product quality of such complex integrated circuits before shipping them to final users, extensive manufacturing tests are necessary and the associated test cost can account for a large share of the total production cost. By introducing spare cores on-chip, the burn-in test time can be shortened and the defect coverage requirements for core tests can be also relaxed, without sacrificing quality of the shipped products. If the above test cost reduction exceeds the manufacturing cost of the extra cores, the total production cost of manycore chips can be reduced. In this paper, we develop novel analytical models to study the above tradeoff and we verify the effectiveness of the proposed test economics model for hypothetical manycore chips with various configurations.Index Terms-Analytical model, manycore chip, product quality test economics.

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“…Software schemes have also been proposed to detect permanent hardware faults (e.g., [7,16,22]). These schemes are complimentary to Detouring, which does not provide error detection or diagnosis, but relies on the presence of some error detection mechanism to obtain information about faulty hardware.…”

Section: Software-based Fault Tolerancementioning

confidence: 99%

Detouring: Translating software to circumvent hard faults in simple cores

Meixner

Sorin

2008

2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)

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CMOS technology trends are leading to an increasing incidence of hard (permanent) faults in processors. These faults may be introduced at fabrication or occur in the field. Whereas high-performance processor cores have enough redundancy to tolerate many of these faults, the simple, low-power cores that are attractive for multicore chips do not. We propose Detouring, a software-based scheme for tolerating hard faults in simple cores. The key idea is to automatically modify software such that its functionality is unchanged but it does not use any of the faulty hardware. Our initial implementation of Detouring tolerates hard faults in several hardware components, including the instruction cache, registers, functional units, and the operand bypass network. Detouring has no hardware cost and no performance overhead for fault-free cores.

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Systematic software-based self-test for pipelined processors

Cited by 34 publications

References 24 publications

Application-Aware diagnosis of runtime hardware faults

Application-Aware diagnosis of runtime hardware faults

Economic Analysis of Testing Homogeneous Manycore Chips

Detouring: Translating software to circumvent hard faults in simple cores

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