Systematic development of analog circuit structural macromodels through behavioral model decoupling

Wei, Ying; Doboli, Alex

doi:10.1145/1065579.1065599

Cited by 20 publications

(7 citation statements)

References 13 publications

(19 reference statements)

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“…In the literature, macromodels have been referred to as white-box models that carry a certain amount of physical information of the design, and as black-box models that approximate the circuit behavior. They are typically either simplified structures of the design [22] or analytical equations derived based on the designers' knowledge of the circuit [23,24]. Metamodels, also called surrogate models, are gaining increasing attention in circuit design and are black-box models.…”

Section: Related Prior Researchmentioning

confidence: 99%

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

Mohanty,

Kougianos

2019

Preprint

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Electronic circuit behavioral models built with hardware description/modeling languages such as Verilog-AMS for system-level simulations are typically functional models. They do not capture the physical design (layout) information of the target design. Thus, their applications are limited to early design feasibility studies and/or pre-layout functional verification. Numerous iterations of post-layout design adjustments are usually required to ensure that design specifications are met with the presence of layout parasitics. In this paper a paradigm shift of the current trend is presented that integrates layout-level information (with full parasitics) in Verilog-AMS through metamodels such that systemlevel simulation of a mixed-signal circuit/system is realistic and as accurate as true parasitic netlist simulation. The simulations performed with these parasitic-aware models can be used to estimate system performance without layout iterations. We call this new form of Verilog-AMS as iVAMS (i.e. Intelligent Verilog-AMS). We call this iVAMS 1.0 as it is simple polynomial-metamodel integrated Intelligent Verilog-AMS. As a specific case study, a voltage-controlled oscillator (VCO) Verilog-AMS behavioral model and design flow are proposed to assist fast PLL design space exploration. The PLL simulation employing quadratic metamodels achieves approximately 10× speedup compared to that employing the layout extracted, parasitic netlist. The simulations using this behavioral model attain high accuracy. The observed error for the simulated lock time and average power dissipation are 0.7 % and 3 %, respectively. This behavioral metamodel approach bridges the gap between layout-accurate but fast simulation and design space exploration. The proposed method also allows much shorter design verification and optimization to meet stringent time-to-market requirements. In the PLL optimization case study, 46 % PLL power reduction was achieved using a differential evolution algorithm and the proposed layout-accurate behavioral model. Compared to the optimization using the layout netlist, the runtime using the behavioral model is reduced by 88.9 %. To the best of the authors' knowledge this is the first approach that brings layout-level accuracy to system-level design exploration and is applied towards mixed-signal design exploration.

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Section: Related Prior Researchmentioning

confidence: 99%

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

Mohanty,

Kougianos

2019

Preprint

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“…Macromodeling, starting from an op-amp model in 1974 [31], looks to create a nonlinear model to reproduce circuit responses as close as possible [32] using simpler digital numerical models. Models look to utilize generalized, low-order polynomials around a single fixed operating point [33][34][35][36][37], and some models utilize the nonlinear dynamics of the transistors [29,[38][39][40]. These techniques often are coupled with tool design approach, particularly joint verification of digital and analog systems [41][42][43][44].…”

Section: Level = 2: Enabling Circuit Designers To Build Level = 1 Blocksmentioning

confidence: 99%

Enabling Energy-Efficient Physical Computing through Analog Abstraction and IP Reuse

Hasler

Natarajan

Kim

2018

JLPEA

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This paper shows the first step in analog (and mixed signal) abstraction utilized in large-scale Field Programmable Analog Arrays (FPAA), encoded in the open-source SciLab/Xcos based toolset. Having any opportunity of a wide-scale utilization of ultra-low power technology both requires programmability/reconfigurability as well as abstractable tools. Abstraction is essential both make systems rapidly, as well as reduce the barrier for a number of users to use ultra-low power physical computing techniques. Analog devices, circuits, and systems are abstractable and retain their energy efficient opportunities compared with custom digital hardware. We will present the analog (and mixed signal) abstraction developed for the open-source toolkit used for the SoC FPAAs. Abstraction of Blocks in the FPAA block library makes the SoC FPAA ecosystem accessible to system-level designers while still enabling circuit designers the freedom to build at a low level. Multiple working test cases of various levels of complexity illustrate the analog abstraction capability. The FPAA block library provides a starting point for discussing the fundamental block concepts of analog computational approaches.

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“…Transient simulation, a main tool in AMS verification, generally requires long simulation time and large computing resources. Simulation time can be reduced by using behavioral models of the circuits [9,10,11]. Existing behavioral modeling methods include black box modeling [12,13], white box or structural modeling [10,11], base-band modeling, and event-driven modeling [14].…”

Section: Related Workmentioning

confidence: 99%

Causal reasoning mining approach to analog circuit verification

Jiao

Doboli

2016

Integration

Self Cite

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Functional errors in analog portion of mixed signal circuits become more severe and improvements in verification methods are increasingly important. Current verification methods fall into two categories, simulation-based verification and formal verification [1], focusing on verifying analog circuit function/performance. This paper proposes a novel approach verifying analog circuit design using causal reasoning. Causal reasoning is the inductive reasoning process to create a new design. The flow begins with mining the causal reasoning steps (design plan) that produced the circuit, including starting ideas, design step sequence, and their justifications [2]. Then, topological features corresponding to the starting ideas and design step sequence are verified individually by replacing the related devices with ideal behavior model. Performance is evaluated through Cadence Spectre simulation. Comparison with new circuit performance reveals incorrect functional issues and/or performance potentials for improvement. They are negative causes of certain starting ideas or design steps, which might have been omitted during the design process. The paper discusses three operational amplifier designs realized in 0.2-µm CMOS technology to illustrate the verification approach.

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Systematic development of analog circuit structural macromodels through behavioral model decoupling

Cited by 20 publications

References 13 publications

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization

Enabling Energy-Efficient Physical Computing through Analog Abstraction and IP Reuse

Causal reasoning mining approach to analog circuit verification

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