Systematic Analysis, Design and Optimization of On-Chip Spiral Inductor for Si based RFIC's

Haobijam, Genemala; Paily, Roy

doi:10.1109/indcon.2006.302818

Cited by 2 publications

(4 citation statements)

References 11 publications

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“…This shows that with a small offset the magnetic coupling can be maximized and the inductance to area ratio can be increased. These results are also consistent with the performance trend of planar inductors with layout parameters studied in [21][22][23]. The important characteristic of MPS structure is its symmetrical nature.…”

Section: Performance Trend Of Mps Inductorssupporting

confidence: 86%

Design of multilevel pyramidically wound symmetric inductor for CMOS RFIC’s

Haobijam

Paily

2009

Analog Integr Circ Sig Process

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This paper presents the design of a multilevel pyramidically wound symmetric (MPS) inductor structure. Being multilevel, the MPS inductor achieves high inductance to area ratio and hence occupies smaller silicon area. The symmetric inductor is realized by winding the metal trace of the spiral coil down and up in a pyramidal manner exploiting the multilevel VLSI interconnects technology. Closed form expressions are also developed to estimate the self resonating frequency (f res ) of the MPS inductor and results are compared to two layer conventional symmetric and asymmetric stack. The estimation is also validated with full wave electromagnetic simulation. The performance of various MPS inductors of different metal width, metal offsets and outer diameter is demonstrated. For an inductance of 8 nH, the MPS inductor reduces the area by 65-95% over conventional planar symmetric inductors and 71-94% over its equivalent pair of asymmetric planar inductors. The performance is also compared to other symmetric inductors reported in literature. With MPS inductor, the cost and size of RF IC's will be reduced significantly.

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Section: Performance Trend Of Mps Inductorssupporting

confidence: 86%

Design of multilevel pyramidically wound symmetric inductor for CMOS RFIC’s

Haobijam

Paily

2009

Analog Integr Circ Sig Process

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“…The width was chosen to vary from 5 lm to 25 lm. Several studies [4,7,17] has shown that tight coupling of the magnetic field maximizes the quality factor and reduces the chip area for a given inductor layout. The interwinding capacitance from tighter coupling has only a slight impact on performance .…”

Section: Bounding Of Layout Parametersmentioning

confidence: 99%

“…The technological parameters are substrate resistivity, insulator thickness, conductor thickness and resistance. The dependence of the quality factor and inductance on these parameters has been studied [4][5][6][7]. In [7] the performance trend with the layout parameters was studied keeping the inductance value constant.…”

Section: Introductionmentioning

confidence: 99%

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Efficient optimization of integrated spiral inductor with bounding of layout design parameters

Haobijam

Paily

2007

Analog Integr Circ Sig Process

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In this paper we present an efficient method of determining the optimized layout of on chip spiral inductor. The method initially identifies the feasible region of optimization by developing layout design parameter bound curves for a large range of physical inductance values that satisfies the same area specification. For any desired inductance value the upper and lower bounds of the optimization variables are determined graphically. An enumeration algorithm implemented finds the global optimum layout that gives the highest quality factor in less than 1 s of CPU time with less function evaluations. The optimization method also gives the performance of all possible combinations that results the same inductance value. Subsequently important fundamental tradeoff of the design like quality factor and area, quality factor and inductance, quality factor and operating frequency, maximum quality factor and the peak frequency is explored in few seconds. The method also gives other valuable information such as sensitivity of the inductance and quality factor to the layout design parameters. The accuracy of the proposed method is verified using a 3D electromagnetic simulator.

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Systematic Analysis, Design and Optimization of On-Chip Spiral Inductor for Si based RFIC's

Cited by 2 publications

References 11 publications

Design of multilevel pyramidically wound symmetric inductor for CMOS RFIC’s

Design of multilevel pyramidically wound symmetric inductor for CMOS RFIC’s

Efficient optimization of integrated spiral inductor with bounding of layout design parameters

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