System optimization for OLTP workloads

Kunkel, S.; Armstrong, B.; Vitale, Philip L.

doi:10.1109/40.768504

Cited by 18 publications

(17 citation statements)

References 7 publications

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“…Table 1 also lists the number of coherence misses in an invalidate-based coherence protocol for two cache line sizes: 4 bytes and 128 bytes. Although the number of coherence misses is fairly small for the two scientific applications, these misses have a significant performance impact on commercial applications, as others have observed [6], [31].…”

Section: Methodsmentioning

confidence: 88%

“…These delays are exacerbated in multiprocessor systems where cache misses must navigate multiple levels of interconnect before they are serviced. It has been projected that as cache hierarchies grow larger, other sources of cache misses (conflict and capacity) will be reduced, resulting in an even greater proportion of coherence misses [31].…”

Section: Identifying Unnecessary Coherence Misses Using a Constraint mentioning

confidence: 99%

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Constraint graph analysis of multithreaded programs

Cain

Lipasti

Nair

Oceans 2002 Conference and Exhibition. Conference Proceedings (Cat. No.02CH37362)

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This paper presents a framework for analyzing the performance of multithreaded programs using a model called a constraint graph. We review previous constraint graph definitions for sequentially consistent systems, and extend these definitions for use in analyzing other memory consistency models. Using this framework, we present two constraint graph analysis case studies using several commercial and scientific workloads running on a full system simulator. The first case study illustrates how a constraint graph can be used to determine the necessary conditions for implementing a memory consistency model, rather than conservative sufficient conditions. Using this method, we classify coherence misses as either required or unnecessary. We determine that on average over 30% of all load instructions that suffer cache misses due to coherence activity are unnecessarily stalled because the original copy of the cache line could have been used without violating the memory consistency model. Based on this observation, we present a novel delayed consistency implementation that uses stale cache lines when possible. The second case study demonstrates the effects of memory consistency constraints on the fundamental limits of instruction level parallelism, compared to previous estimates that did not include multiprocessor constraints. Using this method we determine the differences in exploitable ILP across memory consistency models for processors that do not perform consistency-related speculation.

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Section: Methodsmentioning

confidence: 88%

Section: Identifying Unnecessary Coherence Misses Using a Constraint mentioning

confidence: 99%

Constraint graph analysis of multithreaded programs

Cain

Lipasti

Nair

Oceans 2002 Conference and Exhibition. Conference Proceedings (Cat. No.02CH37362)

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“…There are several other contemporary processor designs that are specifically focused on commercial markets [5,23]. 7 Several papers from Stanford have advocated and evaluated the use of chip multiprocessing (CMP) in the context of workloads such as SPEC [15,29,33], and the Hydra project is exploring CMP with a focus on thread-level speculation [16,17].…”

Section: Discussion and Related Workmentioning

confidence: 99%

Piranha: a scalable architecture based on single-chip multiprocessing

Barroso¹,

Gharachorloo²,

McNamara³

et al.

Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201)

184

281

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The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limits of instructionlevel parallelism. Meanwhile, such designs are especially ill suited for important commercial applications, such as on-line transaction processing (OLTP), which suffer from large memory stall times and exhibit little instruction-level parallelism. Given that commercial applications constitute by far the most important market for high-performance servers, the above trends emphasize the need to consider alternative processor designs that specifically target such workloads. The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising approach for designing processors targeted at commercial servers. This paper describes the Piranha system, a research prototype being developed at Compaq that aggressively exploits chip multiprocessing by integrating eight simple Alpha processor cores along with a two-level cache hierarchy onto a single chip. Piranha also integrates further on-chip functionality to allow for scalable multiprocessor configurations to be built in a glueless and modular fashion. The use of simple processor cores combined with an industry-standard ASIC design methodology allow us to complete our prototype within a short time-frame, with a team size and investment that are an order of magnitude smaller than that of a commercial microprocessor. Our detailed simulation results show that while each Piranha processor core is substantially slower than an aggressive next-generation processor, the integration of eight cores onto a single chip allows Piranha to outperform next-generation processors by up to 2.9 times (on a per chip basis) on important workloads such as OLTP. This performance advantage can approach a factor of five by using full-custom instead of ASIC logic. In addition to exploiting chip multiprocessing, the Piranha prototype incorporates several other unique design choices including a shared second-level cache with no inclusion, a highly optimized cache coherence protocol, and a novel I/O architecture.

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“…Previous studies of commercial workloads have demonstrated the importance of optimizing cache-to-cache transfers due to the high percentage of cache misses to lines resident in the caches of other processors [2,15,17,22]. We present a breakdown of cache misses based on the location from where they are serviced in the S80 memory system.…”

Section: Cache-to-cache Transfersmentioning

confidence: 99%

“…These benchmarks have been very useful for gauging the absolute performance and price/performance of combined software/hardware systems. A significant body of prior work has studied the architectural requirements of such workloads [13,15,17,19,20,22]. At the same time, the Systems Performance Evaluation Cooperative (SPEC), a similar consortium, has developed standard benchmarks for evaluating both static and dynamic web content serving (SPECweb96 and SPECweb99, respectively) [26].…”

Section: Introductionmentioning

confidence: 99%