System on chip with 1.12mW-32Gb/s AC-coupled 3D memory interface

Canegallo, R.; Perugini, L.; Pasini, Alessandro; Innocenti, M.; Scandiuzzo, M.; Guerrieri, R.; Rolandi, P.L.

doi:10.1109/cicc.2009.5280782

Cited by 6 publications

(3 citation statements)

References 9 publications

(7 reference statements)

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“…Data rates are usually very high (Myat et al's [8]). It is possible to use grids of channels in parallel: 260 Gb/s using 144 channels [9] and 32 Gb/s using 128 channels [10]. Capacitive coupling rarely supports distances over 10 µm.…”

Section: Wireless Technologiesmentioning

confidence: 99%

“…Figure 1 collates data from a number of studies in the three aforementioned technologies. Figure 1a plots capacitive coupling technologies [8,10,[20][21][22][23], Figure 1b summaries inductive coupling [13,[24][25][26][27][28] and Figure 1c belongs to mm-wave on-chip radios [29][30][31][32][33][34][35][36][37]. Figure 1 shows that the energy consumption in all three categories have dropped over the last 15 years.…”

Section: J Sens Actuator Netw 2018 7 X For Peer Review 3 Of 19mentioning

confidence: 99%

See 1 more Smart Citation

Performance Analysis of a 3D Wireless Massively Parallel Computer

Sarvestani

Bailey

Austin

2018

JSAN

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In previous work, the authors presented a 3D hexagonal wireless direct-interconnect network for a massively parallel computer, with a focus on analysing processor utilisation. In this study, we consider the characteristics of such an architecture in terms of link utilisation and power consumption. We have applied a store-and-forward packet-switching algorithm to both our proposed architecture and a traditional wired 5D direct network (the same as IBM's Blue Gene). Simulations show that for small and medium-size networks the link utility of the proposed architecture is comparable with (and in some cases even better than) traditional 5D networks. This work demonstrates that there is a potential for wireless processing array concepts to address High-Performance Computing (HPC) challenges whilst alleviating some significant physical construction drawbacks of traditional systems.

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Section: Wireless Technologiesmentioning

confidence: 99%

Section: J Sens Actuator Netw 2018 7 X For Peer Review 3 Of 19mentioning

confidence: 99%

Performance Analysis of a 3D Wireless Massively Parallel Computer

Sarvestani

Bailey

Austin

2018

JSAN

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show abstract

“…Concerning voltage driven capacitive coupling, only face-to-face stacking is allowed to guarantee sufficient inter-chip coupling. Although the number of tiers is limited to two in this method, it consumes less power and occupies less chip area, which enables high interconnect density [4]. Several capacitive-coupling-based transceivers such as unidirectional and bi-directional transceivers have been presented [5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%