System-level power estimation tool for embedded processor based platforms

Rethinagiri, Santhosh Kumar; Palomar, Oscar; Atitallah, Rabıe Ben; Niar, Smaïl; Unsal, Osman S.; Kestelman, Adrián Cristal

doi:10.1145/2555486.2555491

Cited by 46 publications

(23 citation statements)

References 18 publications

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“…In Step 3 (described in Section VI) we describe our robust model formulation where we use our knowledge of how power is consumed in CPUs, as opposed to adding regression coefficients directly to PMC data as is typical in existing works [11], [20], [21], [24]. Our formulation reduces multicollinearity, separates dynamic and static power consumption, works with any given voltage and frequency, and, when combined with the added model stability, allows the model building experiment duration to be reduced by 100× while trading off only 0.6% error.…”

Section: Proposed Methodologymentioning

confidence: 99%

“…In [10] significant sources of errors are found in McPAT which are largely caused by abstraction error. Rethinagiri et al [11] show McPAT to have average power errors of over 20% for most of the tested workloads when comparing McPAT to a physical ARM Cortex-A9 device. Bottom-up power models are generally unsuitable for run-time management applications due to their relatively poor accuracy and large computational complexity.…”

Section: Related Workmentioning

confidence: 97%

“…This is due to the lack of a known method of extracting PMCs on mobile platforms, where there are more technical challenges in doing so. Rethinagiri et al [11] also highlight the scarcity of fast power modeling work for mobile systems and present a tool for system-level power estimation created by using a performance simulator, to provide simulated PMC data, with real measured power data from a development board. To overcome the difficulties in obtaining PMC data, simple CPU utilization has been used to make energy-aware run-time scheduling decisions in an ARM big.LITTLE architecture [26].…”

Section: Cpu Voltage Modelmentioning

confidence: 99%

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Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs

Walker

Diestelhorst

Hansson

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

105

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Abstract-Modern mobile and embedded devices are required to be increasingly energy-efficient while running more sophisticated tasks, causing the CPU design to become more complex and employ more energy-saving techniques. This has created a greater need for fast and accurate power estimation frameworks for both run-time CPU energy management and design-space exploration. We present a statistically rigorous and novel methodology for building accurate run-time power models using Performance Monitoring Counters (PMCs) for mobile and embedded devices, and demonstrate how our models make more efficient use of limited training data and better adapt to unseen scenarios by uniquely considering stability. Our robust model formulation reduces multicollinearity, allows separation of static and dynamic power, and allows a 100× reduction in experiment time while sacrificing only 0.6% accuracy. We present a statistically detailed evaluation of our model, highlighting and addressing the problem of heteroscedasticity in power modeling. We present software implementing our methodology and build power models for ARM Cortex-A7 and Cortex-A15 CPUs, with 3.8% and 2.8% average error, respectively. We model the behavior of the nonideal CPU voltage regulator under dynamic CPU activity to improve modeling accuracy by up to 5.5% in situations where the voltage cannot be measured. To address the lack of research utilizing PMC data from real mobile devices, we also present our data acquisition method and experimental platform software. We support this work with online resources including software tools, documentation, raw data and further results.

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Section: Proposed Methodologymentioning

confidence: 99%

Section: Related Workmentioning

confidence: 97%

Section: Cpu Voltage Modelmentioning

confidence: 99%

See 1 more Smart Citation

Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs

Walker

Diestelhorst

Hansson

et al. 2017

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

105

View full text Add to dashboard Cite

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“…In existing works on PMC-based run-time power models, the independent variables (i.e. PMC events and sometimes the CPU voltage (V DD ), the clock frequency (f clk and/or the temperature, T ) are inserted directly into a regression tool [9], [10], [25]- [27]; the relationships between the variables and power consumption are not considered. A recent work [27], which evaluates the state-of-the-art and typifies the general approach, proposes the model equation shown in Equation 1.…”

Section: Regression-based Modelling Methodologymentioning

confidence: 99%

Thermally-aware composite run-time CPU power models

Walker

Diestelhorst

Hansson

et al. 2016

2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Abstract-Accurate and stable CPU power modelling is fundamental in modern system-on-chips (SoCs) for two main reasons: 1) they enable significant online energy savings by providing a run-time manager with reliable power consumption data for controlling CPU energy-saving techniques; 2) they can be used as accurate and trusted reference models for system design and exploration. We begin by showing the limitations in typical performance monitoring counter (PMC) based power modelling approaches and illustrate how an improved model formulation results in a more stable model that efficiently captures relationships between the input variables and the power consumption. Using this as a solid foundation, we present a methodology for adding thermal-awareness and analytically decomposing the power into its constituting parts. We develop and validate our methodology using data recorded from a quad-core ARM Cortex-A15 mobile CPU and we achieve an average prediction error of 3.7% across 39 diverse workloads, 8 Dynamic Voltage-Frequency Scaling (DVFS) levels and with a CPU temperature ranging from 31• C to 91• C. Moreover, we measure the effect of switching cores offline and decompose the existing power model to estimate the static power of each CPU and L2 cache, the dynamic power due to constant background (BG) switching, and the dynamic power caused by the activity of each CPU individually. Finally, we provide our model equations and software tools for implementing in a run-time manager or for using with an architectural simulator, such as gem5. I. INTRODUCTIONWhile mobile devices are required to be ever-more energy efficient, mobile CPU designs are becoming more complex in order to achieve the ever-increasing performance demand of new applications. Key to saving energy is the system's runtime manager (RTM), which controls CPU energy-saving techniques (such as dynamic voltage frequency scaling [DVFS] or heterogeneous cores [e.g. ARM's big.LITTLE technology]) in order to trade off power and performance based on the current conditions and requirements. However, in order to make these trade-offs effectively, run-time knowledge of how power is being consumed is essential. A fast and accurate power model, that is able to predict the current power consumption at runtime, can therefore be used with a run-time manager to make significant energy savings [1].Previously, top-down regression-based models using performance monitoring counters (PMCs) as inputs have been widely shown to be effective in estimating CPU power [2]- [13]. Topdown approaches use power measurements from real devices and predict this measured power using metrics. Therefore they

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“…PETS was initially developed for the evaluation of MPSoC systems [7][8][9]. In ParaDIME, we have extended it to model a variety of other systems, including GPUs [10], DSPs, FPGAs [11] and multi-core (dual-and quad-core) ARM processors [12]. Fig.…”

Section: Heterogeneous Computingmentioning

confidence: 99%

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers

Rethinagiri

Palomar

Sobe

et al. 2015

Microprocessors and Microsystems

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a b s t r a c tDramatic environmental and economic impact of the ever increasing power and energy consumption of modern computing devices in data centers is now a critical challenge. On the one hand, designers use technology scaling as one of the methods to face the phenomenon called dark silicon (only segments of a chip function concurrently due to power restrictions). On the other hand, designers use extreme-scale systems such as teradevices to meet the performance needs of their applications which in turn increases the power consumption of the platform. In order to overcome these challenges, we need novel computing paradigms that address energy efficiency. One of the promising solutions is to incorporate parallel distributed methodologies at different abstraction levels.The FP7 project ParaDIME focuses on this objective to provide different distributed methodologies (software-hardware techniques) at different abstraction levels to attack the power-wall problem. In particular, the ParaDIME framework will utilize: circuit and architecture operation below safe voltage limits for drastic energy savings, specialized energy-aware computing accelerators, heterogeneous computing, energy-aware runtime, approximate computing and power-aware message passing. The major outcome of the project will be a noval processor architecture for a heterogeneous distributed system that utilizes future device characteristics, runtime and programming model for drastic energy savings of data centers. Wherever possible, ParaDIME will adopt multidisciplinary techniques, such as hardware support for message passing, runtime energy optimization utilizing new hardware energy performance counters, use of accelerators for error recovery from sub-safe voltage operation, and approximate computing through annotated code. Furthermore, we will establish and investigate the theoretical limits of energy savings at the device, circuit, architecture, runtime and programming model levels of the computing stack, as well as quantify the actual energy savings achieved by the ParaDIME approach for the complete computing stack with the real environment.

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System-level power estimation tool for embedded processor based platforms

Cited by 46 publications

References 18 publications

Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs

Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs

Thermally-aware composite run-time CPU power models

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers

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