System-level parallelism and throughput optimization in designing reconfigurable computing applications

Abstract

Reconfigurable Computers (RCs) can leverage the synergism between conventional processors and FPGAs to provide low-level hardware functionality at the same level of programmability as general-purpose computers. In a large class of applications, the total I/O time is comparable or even greater than the computations time. As a result, the rate of the DMA transfer between the microprocessor memory and the on-board memory of the FPGA-based processor becomes the performance bottleneck. In this paper, we perform a theoretical and experimental study of this specific performance limitation. The mathematical formulation of the problem has been experimentally verified on the state-of-the art reconfigurable platform, SRC-6E. We demonstrate and quantify the possible solution to this problem that exploits the system-level parallelism within reconfigurable machines. c DMA c c c DMA

FPGA supercomputing platforms: A survey

“…Their work exploited both the fine and coarse-grain parallelism provided by RCs to reach optimal speedup gains. El Araby reported in [20] an order of magnitude speedup over traditional processing techniques.…”

System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance

“…In this paper a study of the system performance on multimedia applications is done. The performance of SRC-GE, a reconfigurable computer, is evaluated in [11]. The platform consists of two general purpose processor boards and a reconfigurable processor board.…”

“…SYSTEM EXECUTION TIME Our main objective in this paper is to find a tradeoff between the buffer size and the system performance. There are some constraints that can affect the system performance; some are forced by system specifications and some are forced by the application nature [11]. The system constraints can be listed in terms of system bus bandwidth, number of concurrent DMA channels and the delay time that elapsed for the interrupt handler procedure in the ARM processor.…”

Accelerating Scientific Applications with the SRC-6 Reconfigurable Computer: Methodologies and Analysis

“…Other application efforts related to the SRC-6 system include an implementation of the DARPA Boolean equation benchmarking suite [16], implementation studies of Triple DES [17], and algorithm implementations for an elliptic curve cryptosystem [18] and a generic wavelet filter [19]. Other research highlighting the system and architecture of the SRC-6 includes a thorough discussion by El-Araby et al on the optimizations used in designing for RC, specifically the SRC-6E [20]. Finally, a paper by Fidanci et al discusses the performance and overhead in the SRC-6 [21].…”