2021
DOI: 10.1007/978-3-030-69244-5_18
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System-Level FPGA Routing for Logic Verification with Time-Division Multiplexing

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“…E-mail: zhangxiaoyan@njnu.edu.cn. A preliminary version of this paper has been presented at the 21st International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2020) [1] . To whom correspondence should be addressed.…”
Section: Introductionmentioning
confidence: 99%
“…E-mail: zhangxiaoyan@njnu.edu.cn. A preliminary version of this paper has been presented at the 21st International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2020) [1] . To whom correspondence should be addressed.…”
Section: Introductionmentioning
confidence: 99%