AbetractThis paper the CAD tools IB8d for systemled design \erificaiion in the AT&T ~~ Di4sion. We discuss features of the tools for huilding and prepring the rrpdel of the systeq for chelopiq teste, for simhtion, for static timing analysis, for resulb analysis, and for circuit conparison
IntroductionThis paper describes some of the CAD tools used for system-level design verification (DV) in the AT&T Computer Division. We discuss features of the tools for building and preparing the model of the system, for developing tests, for simulation, for static timing analysis, for results analysis, and for comparing circuits. The novel tools and tool features include: automatic resistor processing; a language for defining stimuli and simulation control, memory contents and timing specifications; "forced" values for correct handling of bidirectional elements; delay calculation based on physical hierarchy (backplane, board, chip); board-level spike filtering based on a combined inertial and transport delay model; a board-level timing verifier taking into account delay tracking; an "intelligent" trace to help circuit debugging; circuit initialization aids; a circuit equivalence checker that handles clock gating and asynchronous inputs.A companion paper('] presents an overview of the DV system that integrates these tools and discusses the strategy guiding the selection and the use of the tools.
Building the Simulation DatabaseThe simulation database is created directly from the internal representation of the captured schematic. Physical hierarchy (gates, devices, boards, backplanes, etc.) and logical hierarchy (flipflops, registers, memories, ALUs, etc.) are uniformly connected together in this database. A circuit expander allows replacement of alternate implementations of elements without total recompilation. Several levels of modeling detail are provided: gate-level primitives, hardware description language (HDL) models, models written in a programming language (such as C),
P. R Menon
University oj MassachusettsAmherst, M A 01003 and physical models. A consistent connectivity language, defines how all the elements are connected together.
