System-level design guidance using algorithm properties

Guerra, L.M.; Potkonjak, Miodrag; Rabaey, Jan M.

doi:10.1109/vlsisp.1994.574732

Cited by 29 publications

(18 citation statements)

References 12 publications

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“…The system has automated optimizations that it can apply for the designer. It also has estimators [Rab91, Meh94,Gue94] for determining the throughput, area, and power of any of the design versions. Most importantly, it has components for generating design guidance.…”

Section: Methodology Overviewmentioning

confidence: 99%

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A methodology for guided behavioral-level optimization

Guerra

Potkonjak

Rabaey

1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

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-Optimization at the early stages of design are crucial. However, due to an overwhelming number of design and optimization options, design exploration is often conducted in a qualitative, ad-hoc manner. This paper presents a methodology and interactive environment for guiding the exploration process. A prototype targeting behavioral-level optimization for datapath-intensive ASIC implementations has been developed. The key to the approach is encapsulated knowledge about the various optimizations and a set of techniques to automatically extract the "essence" of a design description. At each stage in the exploration process, the system suggests and ranks potential optimizations, both in terms of immediate and longer-term impact. It also provides evaluations of the design and of the likely affects each optimization will have on metrics like power and performance. In the new approach, the designer is responsible for making the actual optimization selections. However, using the provided guidance, designers can make decisions in a more informed manner, and therefore can explore the design solution space more effectively. The effectiveness of the approach is demonstrated on a number of designs. IntroductionTraditionally, concentration has been placed in the development of point tools and methodologies which address a single task within the optimization process. For example, in behavioral-level optimization, in addition to the approaches proposed for partitioning, template matching, and clock selection, there exist more than a hundred transformations [Bac94,Par95]. Some optimizations are restricted to optimization of a specific class of computation (e.g. only linear computations). Some focus on power optimization while others target area or throughput. Furthermore, some concentrate on reduction of just a specific sub-metric; for example, different power optimization techniques have been developed for reducing capacitance, for reducing activity, and for enabling voltage scaling.Effective global optimization, or optimization of a global objective function on current-day complex and heterogeneous applications, clearly requires the coordinated application of a collection of techniques. While many of the problems being addressed by the individual techniques are in themselves computationally intractable, an added layer of complexity clearly exists in deriving an entire optimization trajectory. This added complexity is due to the strong interdependency that exists between techniques. Exploring different trajectories is crucial, as a large variability in attainable improvements exists. Exploring all possible sequences of actions inevitably results in combinatorial explosion, however, and thus is not a feasible option. Furthermore, static scripts are not sufficient since their effectiveness is strongly dependent on the particular design. This paper proposes a methodology for enabling systematic and effective global optimization. The approach involves interactively and quantitatively guiding the designer's exploration pro...

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Section: Methodology Overviewmentioning

confidence: 99%

“…While the work of [Gue94] presents the use of properties for guidance through estimation, in this work, we present a complete environment for their use in guided optimization. Fig.…”

Section: Related Workmentioning

confidence: 99%

A methodology for guided behavioral-level optimization

Guerra

Potkonjak

Rabaey

1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

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“…To strengthen the motivation for block processing, it has been shown that block processing improves regularity and thus reduces the effort in address calculation and context switching [4]. Block processing also facilitates efficient utilization of pipelines for vector-based algorithms, which are common in DSP applications [2].…”

Section: Related Workmentioning

confidence: 99%

Memory-constrained Block Processing for DSP Software Optimization

Shen

Bhattacharyya

2007

J Sign Process Syst Sign Image

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Abstract. Digital signal processing (DSP) applications involve processing long streams of input data. It is important to take into account this form of processing when implementing embedded software for DSP systems. Task-level vectorization, or block processing, is a useful dataflow graph transformation that can significantly improve execution performance by allowing subsequences of data items to be processed through individual task invocations. In this way, several benefits can be obtained, including reduced context switch overhead, increased memory locality, improved utilization of processor pipelines, and use of more efficient DSP oriented addressing modes. On the other hand, block processing generally results in increased memory requirements since it effectively increases the sizes of the input and output values associated with processing tasks. In this paper, we investigate the memory-performance trade-off associated with block processing. We develop novel block processing algorithms that carefully take into account memory constraints to achieve efficient block processing configurations within given memory space limitations. Our experimental results indicate that these methods derive optimal memory-constrained block processing solutions most of the time. We demonstrate the advantages of our block processing techniques on practical kernel functions and applications in the DSP domain.

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“…Previous works dealing with metrics have been completed in the areas of high-level synthesis [9,6] and hardware software codesign [9,18,19]. In [1] the metrics provide algorithm properties regarding a hardware implementation.…”

Section: Metricsmentioning

confidence: 99%

Design of a multimedia processor based on metrics computation

Amor

Moullec

Diguet³

et al. 2005

Advances in Engineering Software

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Media-processing applications, such as signal processing, 2D and 3D graphics rendering, and image compression, are the dominant workloads in many embedded systems today. The real-time constraints of those media applications have taxing demands on today's processor performances with low cost, low power and reduced design delay. To satisfy those challenges, a fast and efficient strategy consists in upgrading a low cost general purpose processor core. This approach is based on the personalization of a general RISC processor core according the target multimedia application requirements. Thus, if the extra cost is justified, the general purpose processor GPP core can be enforced with instruction level coprocessors, coarse grain dedicated hardware, ad hoc memories or new GPP cores. In this way the final design solution is tailored to the application requirements. The proposed approach is based on three main steps: the first one is the analysis of the targeted application using efficient metrics. The second step is the selection of the appropriate architecture template according to the first step results and recommendations. The third step is the architecture generation. This approach is experimented using various image and video algorithms showing its feasibility.Key words: design space exploration, media processor, graph-based specification, guidance, metrics 1-IntroductionWe are currently experiencing an important increase in the use of embedded devices with powerful multimedia capabilities such as speech analysis and synthesis, character recognition, video compression, and graphics animation. Due to the various needs of such applications, embedded devices have to handle various data types and various complex tasks under hard real-time constraints. The need for real-time processing of complex algorithms is further accentuated by the increasing interest in other new domains like 3D image. Especially in the domain of embedded systems, the main design constraint is the time to market priority since the availability of a new product at short time even not perfectly optimised is the key point for its commercial success. Another important point in this domain is the opportunity to take advantage of the application characteristics in order to optimize the energy / time / QoS tradeoff. Thus, our strategy is to define a framework that provides a simple and fast analysis tool. The first point is to start with a typical software specification which is automatically transformed into a graph-based internal representation. The idea is to take as an input a standard code without performing any additional effort and to analyze it. Even if the false data dependencies have been eliminated, the resulting hierarchical graph still reflects the designer or standard authors point of view. If such a specification fits with a low cost, low power embedded processor, this is probably the more interesting solution. Secondly, our objective is to extract from the various granularity levels of this specification opportunities of paralleli...

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System-level design guidance using algorithm properties

Cited by 29 publications

References 12 publications

A methodology for guided behavioral-level optimization

A methodology for guided behavioral-level optimization

Memory-constrained Block Processing for DSP Software Optimization

Design of a multimedia processor based on metrics computation

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