System level design and optimization of single-loop CT sigma-delta modulators for high resolution wideband applications

Pakniat, Hossein; Yavari, Mohammad

doi:10.1016/j.mejo.2015.08.010

Cited by 6 publications

(3 citation statements)

References 22 publications

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“…Another nonideality, which can degrade the performance of the CT IΣ∆ ADC is the clock jitter. The clock jitter restricts the maximum value of OSR in CT modulators with both NRZ and return‐to‐zero (RZ) DACs . A random Gaussian noise with a variance of

σ_{j}^{2}

is modeled as the clock jitter.…”

Section: Proposed Adaptive Ct Iς∆ Adcmentioning

confidence: 99%

“…The clock jitter restricts the maximum value of OSR in CT modulators with both NRZ and return-to-zero (RZ) DACs. 21 A random Gaussian noise with a variance of σ 2 j is modeled as the clock jitter. The in-band-noise (IBN) due to the clock jitter in a CT IΣΔ modulator with an NRZ DAC is given by the following 16 :…”

Section: Effect Of Eld and Clock Jitter In Ct Iσδ Adcmentioning

confidence: 99%

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An adaptive continuous‐time incremental Σ∆ ADC for neural recording implants

Barati

Yavari

2018

Circuit Theory & Apps

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Summary In this paper, an analog‐to‐digital converter (ADC) with adaptive resolution is presented for wireless neural recording implants. The resolution of the ADC is changed according to the neural signal content, and for this purpose, a continuous‐time (CT) incremental sigma‐delta (IΣ∆) modulator is employed. The ADC digitizes the action potential (AP) and background noise (B‐noise) with 8‐bit and 3‐bit resolutions, respectively. An automatic AP detector is used to separate the APs from the B‐noise in order to select one of the two proportional resolutions. The power dissipation and output data rate of the ADC are reduced by using this technique. Analytical calculations and behavioral simulation results are provided to evaluate the performance of the proposed ADC. To further confirm its efficiency, the circuit‐level implementation of the CT IΣ∆ ADC is presented in Taiwan Semiconductor Manufacturing Company (TSMC) 90‐nm complementary metal‐oxide semiconductor (CMOS) process. According to the simulation results, the proposed ADC achieves 8‐bit or 3‐bit resolution adaptively with 10 kHz bandwidth while the average power consumption is less than 1.89 μW from a single 1‐V power supply.

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σ_{j}^{2}

is modeled as the clock jitter.…”

Section: Proposed Adaptive Ct Iς∆ Adcmentioning

confidence: 99%

Section: Effect Of Eld and Clock Jitter In Ct Iσδ Adcmentioning

confidence: 99%

An adaptive continuous‐time incremental Σ∆ ADC for neural recording implants

Barati

Yavari

2018

Circuit Theory & Apps

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“…Recently, the usage of continuous‐time delta‐sigma modulators (CTDSMs) in wideband and power‐efficient high‐resolution applications is very high when compared to discrete‐time delta‐sigma modulator (DTDSM) due to its intrinsic advantages in antialiasing filtering and power efficiency [1]. However, the realisation of CTDSM is more complex for achieving larger resolution at higher frequencies with less power [2].…”

Section: Introductionmentioning

confidence: 99%

Efficient CTDSM based on GM‐C quantiser and improved dynamic element matching

Sahu¹,

Chandra

Sinha

et al. 2020

IET Circuits, Devices & Systems

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In this study, a continuous-time delta-sigma modulator (CTDSM) is developed using a Gm-C based noise-shaping quantiser (Gm-C-NSQ) with an improved dynamic element matching (i-DEM) algorithm. Here, a Gm-C integrator is used to develop NSQ, since it increases the effectiveness of the proposed modulator in terms of power consumption and die area. This Gm-C-NSQ uses only three dynamic latches to provide efficient quantisation level and to increase the order of noise shaping. Moreover, an i-DEM algorithm is utilised to reduce the non-linearities of the quantiser and mismatching error of the digital-toanalogue converters presented in the feedback structure of the modulator. Here, an 180 nm CMOS technology is used to design the proposed modulator and it functions at 2.6 MHz sampling frequency. Simulation results show that the proposed modulator can achieve a peak spurious-free dynamic range (SFDR) of 93.67 dB and a peak signal-to-noise ratio of 87.38 dB for 20 kHz signal bandwidth. Furthermore, the proposed modulator consumes 0.0863 mW power when 1.2 V supply voltage is applied.

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