System Architecture and Implementation of MIMO Sphere Decoders on FPGA

Huang, Xinming; Cao, Liang; Ma, Jingjing

doi:10.1109/tvlsi.2007.912042

Cited by 44 publications

(41 citation statements)

References 21 publications

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“…To achieve close to Maximum Likelihood (quasi-ML) performance, the detection complexity scales in a super-linear fashion. A substantial body of work has addressed the design of embedded detectors which employ Sphere Decoding (SD) algorithms [4], [5], [6] for this operation, motivated directly by the ability of SD algorithms to enable quasi-ML detection performance for relatively small MIMO topologies of 2, 4 or 8 antennas.…”

Section: Introductionmentioning

confidence: 99%

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FPGA-based Tabu search for detection in large-scale MIMO systems

McAllister

2014

2014 IEEE Workshop on Signal Processing Systems (SiPS)

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Section: Introductionmentioning

confidence: 99%

“…The use and realisation of linear and SD algorithms is very well studied, see e.g. [1], [7], [6], [5], [4]. The use of heuristic approaches is not so well developed.…”

Section: Introductionmentioning

confidence: 99%

FPGA-based Tabu search for detection in large-scale MIMO systems

McAllister

2014

2014 IEEE Workshop on Signal Processing Systems (SiPS)

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“…1145/2490830 usage and computation speed with respect to conventional blocks [Gustafsson 2007;Xu et al 2008]. However, in some applications, these constants may change in certain time steps, which prevents the use of standard constant multipliers [Bosí et al 1999;Bouganis et al 2009;Huang et al 2008;Shoufan et al 2010]. Some researchers [Chen and Chang 2009;Demirsoy et al 2007;Turner and Woods 2004] have addressed this problem when the constant changes to several predefined values, as it does in FFT, DCT, filters, and many others.…”

Section: Introductionmentioning

confidence: 99%

Self-Reconfigurable Constant Multiplier for FPGA

Hormigo

Caffarena

Oliver

et al. 2013

ACM Trans. Reconfigurable Technol. Syst.

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Constant multipliers are widely used in signal processing applications to implement the multiplication of signals by a constant coefficient. However, in some applications, this coefficient remains invariable only during an interval of time, and then, its value changes to adapt to new circumstances. In this article, we present a self-reconfigurable constant multiplier suitable for LUT-based FPGAs able to reload the constant in runtime. The pipelined architecture presented is easily scalable to any multiplicand and constant sizes, for unsigned and signed representations. It can be reprogrammed in 16 clock cycles, equivalent to less than 100 ns in current FPGAs. This value is significantly smaller than FPGA partial configuration times. The presented approach is more efficient in terms of area and speed when compared to generic multipliers, achieving up to 91% area reduction and up to 102% speed improvement for the case-study circuits tested. The power consumption of the proposed multipliers are in the range of those of slice-based multipliers provided by the vendor.

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“…FPGA is another popular platform that can meet high data rate requirements. Huang et al [11] prototyped a 4 × 4 16-QAM detector on a Xilinx FPGA device with a throughput of 81.5 Mbps and 36.1 Mbps based on Schnorr-Euchner (SE) and Viterbo-Boutros (VB) algorithm respectively. Software based designs are another viable alternative but typically do not meet performance requirements.…”

Section: Introductionmentioning

confidence: 99%

Implementation of a High Throughput Soft MIMO Detector on GPU

Sun

Gupta

et al. 2010

J Sign Process Syst

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Multiple-input multiple-output (MIMO) significantly increases the throughput of a communication system by employing multiple antennas at the transmitter and the receiver. To extract maximum performance from a MIMO system, a computationally intensive search based detector is needed. To meet the challenge of MIMO detection, typical suboptimal MIMO detectors are ASIC or FPGA designs. We aim to show that a MIMO detector on Graphic processor unit (GPU), a low-cost parallel programmable co-processor, can achieve high throughput and can serve as an alternative to ASIC/FPGA designs. However, careful architecture aware software design is needed to leverage the performance offered by GPU. We propose a novel soft MIMO detection algorithm, multi-pass trellis traversal (MTT), and show that we can achieve ASIC/FPGAlike performance and handle different configurations in software on GPU. The proposed design can be used to accelerate wireless physical layer simulations and to offload MIMO detection processing in wireless testbed platforms.

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System Architecture and Implementation of MIMO Sphere Decoders on FPGA

Cited by 44 publications

References 21 publications

FPGA-based Tabu search for detection in large-scale MIMO systems

FPGA-based Tabu search for detection in large-scale MIMO systems

Self-Reconfigurable Constant Multiplier for FPGA

Implementation of a High Throughput Soft MIMO Detector on GPU

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