Synthesizing reconfigurable sequential machines using Tabular models

Rath, Kamlesh; Li, Jian

doi:10.1007/3-540-64359-1_672

Cited by 3 publications

(3 citation statements)

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“…These include DFGs [40], mixed control data-flow graphs (CDFG) [38], timed decision tables (TDT) [33], and various flavors of graph-based and table-based formalisms sometimes augmented with global flow information such as module call graphs (MCG). Although these representations capture common features such as data and control dependencies among operations [29], they are not able to capture the temporal or functional locality among operations as well as the interconfiguration relationships.…”

Section: The Design Modelmentioning

confidence: 99%

“…Rath et al [33] used an intermediate tabular model called the TDT to separate the control and data-path and to divide the data-path into different control paths. A TDT representation of system behavior consists of three major parts: (1) a control section which is a set of rules, or a list of control path segments; (2) a delay table which lists the execution delay of each action or data-path operation in the model; and (3) an additional table describing the data-dependency, serialization and concurrency type specified between each pair of operations.…”

Section: Design Models For Dynamically Reconfigurable Systemsmentioning

confidence: 99%

“…The subgraphs identified by the partitioning step form the different configurations that can be swapped in and out of the DR FPGAs. However, the synthesis method described in [33] is only suitable for designing fully reconfigurable and control-dominated systems, as the TDT expressions will not be able to capture the inter-configuration relations and data-flow boundaries that are present in high-level descriptions. Another limitation of their approach is that they analyze and partition the system specification at synthesis-time and not at run-time.…”

Section: Design Models For Dynamically Reconfigurable Systemsmentioning

confidence: 99%

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A review of high-level synthesis for dynamically reconfigurable FPGAs

Zhang

2000

Microprocessors and Microsystems

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Dynamically Reconfigurable Field Programmable Gate Arrays (DR FPGAs) change many of the basic assumptions of what hardware is. DR FPGA-based dynamically reconfigurable computing has become a powerful methodology for achieving high performance while minimizing the resource required in the implementation of many applications. The key to harnessing the power of DR FPGAs for most applications is to develop high-level synthesis tools for transforming automatically an algorithmic level behavioral specification into DR FPGA configurations. In this paper we survey the current state-of-the-art in high-level synthesis techniques for dynamically reconfigurable systems. The differences in high-level synthesis technology between classical systems and dynamically reconfigurable systems are discussed. Then, we describe the basic tasks in the high-level synthesis of dynamically reconfigurable systems. Finally, techniques that have been developed in the past few years for the high-level synthesis of dynamically reconfigurable systems are presented. ᭧

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Section: The Design Modelmentioning

confidence: 99%

Section: Design Models For Dynamically Reconfigurable Systemsmentioning

confidence: 99%

Section: Design Models For Dynamically Reconfigurable Systemsmentioning

confidence: 99%

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