Synthesis of networks on chips for 3D systems on chips

Abstract

Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (NoCs) are necessary to efficiently handle the 3D interconnect complexity. Designing power efficient NoCs for 3D SoCs that satisfy the application performance requirements, while satisfying the 3D technology constraints is a big challenge. In this work, we address this problem and present a synthesis approach for designing power-performance efficient 3D NoCs. We present methods to determine the best topology, compute paths and perform placement of the NoC components in each 3D layer. We perform experiments on varied, realistic SoC benchmarks to validate the methods and also perform a comparative study of the resulting 3D NoC designs with 3D optimized mesh topologies. The NoCs designed by our synthesis method results in large interconnect power reduction (average of 38%) and latency reduction (average of 25%) when compared to traditional NoC designs.

Floorplanning and topology generation for application-specific Network-on-Chip

“…The next set of benchmarks are obtained from [6]: 263decmp3dec, 263encmp3dec and mp3encmp3dec. The last benchmark is obtained from [8]: D 38 tvopd. Fig.6 shows two floorplan generated for the 263decmp3dec and D 38 tvopd benchmark.…”

“…For regular Noc topology design, some existing NoC solutions assume a mesh-based NoC architecture [4,5], and their focus is on the mapping problem. For application-specific topology design, the design challenges are different in terms of irregular core sizes, various core locations, and different communication flow requirements [6,7,8,9,10]. Most SoCs are typically composed of heterogeneous cores and the core sizes are highly non-uniform.…”

Application-specific 3D Network-on-Chip design using simulated allocation

“…Our algorithm 3D-SAL-FP improves upon the previous algorithms in [14,15] by: 1) using a more sophisticated traffic flow routing algorithm (SAL), 2) adding a feedback loop of floorplanning and NoC synthesis to refine the NoC architecture, 3) using a more accurate switch delay model including the effects of queueing delay and network contention. To show the separate impact of these techniques on the NoC design, we have implemented three other 3D NoC synthesis algorithms.…”

“…Murali et al [15] propose a 3D NoC topology synthesis algorithm, which is an extension to their previous 2D work [19], described above. The 3D NoC synthesis problem has been shown to be NP-hard in [21].…”

“…However, most modern SoC architectures consist of heterogenous cores such as CPU or DSP modules, video processors, and embedded memory blocks, and the traffic requirements among the cores can vary widely. Therefore, regular topologies such as meshes may have significant area and power overhead [14,15], and tuning the topology for application-specific solutions can provide immense benefits.…”