Synthesis of multiplier-less FIR filters with minimum number of additions

Mehendale, Mahesh; Sherlekar, S.D.; Venkatesh, G.

doi:10.1109/iccad.1995.480201

Cited by 50 publications

(63 citation statements)

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“…Many other successful approaches exist, in particular those based on multiple constant multiplication (MCM) using the transpose form (where the registers are on the output path). [11], [12], [13], [14], [15]. A technique called Distributed Arithmetic, which predates FPGA [16], can be considered a generalization of the KCM technique to the MCM problem.…”

Section: Resultsmentioning

confidence: 99%

Sum-of-product architectures computing just right

Dinechin

Istoan

Massouri

2014

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

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Abstract-Many digital filters and signal-processing transforms can be expressed as a sum of products with constants (SPC). This paper addresses the automatic construction of low-precision, but high accuracy SPC architectures: these architectures are specified as last-bit accurate with respect to a mathematical definition. In other words, they behave as if the computation was performed with infinite accuracy, then rounded only once to the low-precision output format. This eases the task of porting double-precision code (e.g. Matlab) to low-precision hardware or FPGA. The paper further discusses the construction of the most efficient architectures obeying such a specification, introducing several architectural improvements to this purpose. This approach is demonstrated in a generic, open-source architecture generator tool built upon the FloPoCo framework. It is evaluated on Finite Impulse Response filters for the ZigBee protocol.

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Section: Resultsmentioning

confidence: 99%

Sum-of-product architectures computing just right

Dinechin

Istoan

Massouri

2014

2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors

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“…The Bull-Horrocks modified (BHM) algorithm and n-dimensional reduced adder graph (RAGn) algorithm, presented in [17], reduce the number of LOs further. Graphrepresentation-based techniques reduce the number of LOs required to implement an MB compared to the CSE methods in [2], [4], [5], and [9]. However, the LDs of the resulting coefficient multipliers are considerably high.…”

Section: Existing Methodsmentioning

confidence: 99%

“…The number of super subexpressions grows with the word length; hence, it is useful only for filter coefficients of higher word lengths. Routing complexity is also high in [20] as compared to [2], [4]- [6], and [9]. Common subexpression elimination (SBE) comes in two varieties, a horizontal CS (HCS) type existing within a coefficient, and a vertical CS (VCS) type existing across the coefficients.…”

Section: Existing Methodsmentioning

confidence: 99%

“…As can be noticed in matrix B (refer to (4)) for i=1, the maximum magnitude is 10 when j=4 and j=6. Similarly, for i=3 and j= (2,4), the maximum magnitude is 10. This means bit 1 can be used to make a subexpression with bit 4 and bit 6, and bit 3 with bit 2 and bit 4.…”

Section: Proposed Cse Methodsmentioning

confidence: 99%

“…The author attempts to minimize the number of adder and delay combinations. In [2], an algorithm is proposed for searching the nonzero 2-bit subexpression from the CSD representation of the coefficients.…”

Section: Existing Methodsmentioning

confidence: 99%

See 2 more Smart Citations

An Improved Non-CSD 2-Bit Recursive Common Subexpression Elimination Method to Implement FIR Filter

Hassan¹

2011

ETRI J

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The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two-bit common subexpression (CS) can be located recursively in a noncanonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.

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