Synthesis of Multi-valued Literal Using Lukasiewicz Logic

Surhonne, Anmol; Bhattacharjee, Debjyoti; Chattopadhyay, Anupam

doi:10.1109/ismvl.2018.00043

Cited by 5 publications

(5 citation statements)

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“…The structure of such a PLA is depicted in Figure 3. a (0) a (1) a (2) a (3) a (4) a (5) a (6) a (7) a (8) a (9) a (10) a (11) a (12) a (13) a (14) a (15) a (16) a (17) a (18) a (19) a (20) a (21) a (22) a (23) a (24) a (25) a (26) M L As one can see, it is composed of two blocks that are memory and logic block. The PLA has 27 inputs that are linked with the memory block and three inputs for function variables x1, x2, and x3 that are the inputs of the logic block.…”

Section: Logic Design Of Multi-valued Circuitmentioning

confidence: 99%

“…Based on these problems, there are tendencies to consider other approaches that do not focus only on binary data. One such approach is known as multiple-valued logic (MVL), which works with more than two values and thus allows encoding more information in "multi-valued bit" than in case of binary-valued bit in two-valued logic [1,5].In the development of the new innovative approach in computer design, the two main pieces of research should be considered. First of them is technological aiming at the development of new multi-valued logic gates.…”

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Application of Generalized Reed–Muller Expression for Development of Non-Binary Circuits

et al. 2019

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Semiconductor devices and binary information technology reach their limits set by the atomic size of miniaturization, calculation speed, and the fundamental principle of energy dissipation per bit processing. Therefore, new technologies in logic design and mathematical approaches must be investigated. Application of multiple-valued logic (MVL) in logic design allows developing gates and circuits with more than two stable states. This enables packing an unprecedented high-density of information. Based on this idea, a new technique of the programmable logic arrays (PLA) construction based on MVL units is considered. The unique aspect of this technique is the application of recurrent generalized Reed-Muller expression (GRME) for MVL function representation. The recurrent procedure for this expression's construction is considered and applied in the PLA development. The proposed structure of PLA consists of two blocks that are memory and logic block. In this paper, we also consider the possibility to use the ferroelectrics for the implementation of cells of the memory block of PLA. The development of gates with multi-stable states is possible by the ferroelectrics ability to pin the polarization as a sequence of stable states.Electronics 2020, 9, 12 2 of 14 is required. This is caused by the limitation of the binary data amount that can be transferred. Based on these problems, there are tendencies to consider other approaches that do not focus only on binary data. One such approach is known as multiple-valued logic (MVL), which works with more than two values and thus allows encoding more information in "multi-valued bit" than in case of binary-valued bit in two-valued logic [1,5].In the development of the new innovative approach in computer design, the two main pieces of research should be considered. First of them is technological aiming at the development of new multi-valued logic gates. Another one is mathematical, which deals with the development of new methods based on MVL in logic design. The acceptance and usage of semiconductor technology in computer design was due to the help of the appropriate mathematical tools that were introduced in binary logic, which started with the early work of G. Boole [6] and C.E. Shannon [7]. Its results have been used for the development of methods of logic synthesis in nanotechnology [8,9]. In the case of MVL design, the main priority has been devoted to elaborate logic gates based on 3-valued logic because logic with this radix, i.e., with radix 3, results in almost minimal complexity of multi-valued based hardware [1]. Because of that, this type of logic is also considered in this paper.There were two first independent investigations in multiple-valued logic about 1920 conducted by E. Post [10] and J. Lukasiewicz [11]. However, the fist algebra that was functionally complete for any radix was the Post's algebra. This algebra is based on a totally ordered set M of elements 0 < 1 < . . . < m − 1 and it has defined operations maximum (MAX) that is OR in binary algebra, minimum (...

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Section: Logic Design Of Multi-valued Circuitmentioning

confidence: 99%

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confidence: 99%

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Application of Generalized Reed–Muller Expression for Development of Non-Binary Circuits

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“…The first level is connected to the memory of PLA to read the coefficients. x2 x1 a (0) a (1) a (2) a (3) a (4) a (5) a (6) a (7) a (8) a (9) a (10) a (11) a (12) a (13) a (14) a (15) a (16) a (17) a (18) a (19) a (20) a (21) a (22) a (23) a (24) a (25) a (26) M L Figure 4. The detailed structure of the PLA for implementation of 3-valued function on 3 variables…”

Section: Multi-valued Logic Circuit Designmentioning

confidence: 99%

“…These factors point on the necessity to design the principally new computing circuits using the Multiple-Valued Logic (MVL) architecture. The primary advantage of MVL is the ability to encode more information per variable ("multi-valued bit") [1,5]. However, in this case, one should go beyond the conventional material technology of semiconducting transistor, having only two stable states, "on" or "off".…”

Section: Introductionmentioning

confidence: 99%

Ferroelectric multiple-valued logic units

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Employing many-valued logic (MVL) data processing allows to dramatically increase the performance of computing circuits. Here we propose to employ ferroelectrics for the material implementation of MVL units basing on their ability to pin the polarization as a sequence of multi-stable states. Two conceptual ideas are considered. As the first system, we suggest using the strained ferroelectric films that can host the polarization states, allowing the effective field-induced multilevel switching between them. As the second one, we propose to employ the ferroelectric nano-samples that confine the topologicallyprotected polarization textures which may be used as MVL structural elements. We demonstrate that these systems are suitable for engineering of the 3-, 4-and even 5-level logic units and consider the circuit design for such elements.

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