Synthesis and Optimization of FPGA-Based Systems

Computing Sorted Subsets for Data Processing in Communicating Software/Hardware Control Systems

“…Since N may have very large value (millions of items) it cannot be processed completely in hardware due to the unavailability of sufficient resources. It is shown in [10,11] [11] permit significantly larger number of items (exceeding thousands of 32-bit items) to be processed and they will be used for computing sorted subsets in hardware. However, in practical cases the given sets anyhow cannot be entirely processed and computing the maximum and/or minimum sorted subsets needs to be done sequentially, nevertheless handling many items in parallel.…”

“…Sorting network At the first step, the first K M-bit data items are sorted in the network [11] which processes L max +K+L min data items but comparators linking the upper part (handling L max M-bit data items) and the lower part (handling L min M-bit data items) are deactivated (i.e. the links with the upper and bottom parts are broken).…”

“…the network from [11] handles L max +K+L min items, but the feedback copying (see the first step and Fig. 3) is disabled.…”

“…5 indicates undefined value. The iterative sorting network is exactly the same as in [11]. Any comparator is shown in Knuth notation [13] and it converts two-item inputs in two-item outputs in such a way that the upper value is greater than or equal to the lower value.…”

“…Any comparator is shown in Knuth notation [13] and it converts two-item inputs in two-item outputs in such a way that the upper value is greater than or equal to the lower value. The maximum number of iterations for sorting is K/2 [14] and this number is almost always smaller because the method [11] terminates subsequent iterations as soon as all items are sorted. There are 3 steps in Fig.…”