SynFull: Synthetic traffic models capturing cache coherent behaviour

Badr, Mario; Jerger, Natalie Enright

doi:10.1109/isca.2014.6853236

Cited by 31 publications

(31 citation statements)

References 42 publications

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“…We then tested out designs using SynFull [5] workloads. Finally, we looked at Full-System simulations using a cycle-accurate multi-core processor simulator.…”

Section: Methodsmentioning

confidence: 99%

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Enabling interposer-based disintegration of multi-core processors

Kannan

Jerger

Loh

2015

Proceedings of the 48th International Symposium on Microarchitecture

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123

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Silicon interposers enable high-performance processors to integrate a significant amount of in-package memory, thereby providing huge bandwidth gains while reducing the costs of accessing memory. Once the price has been paid for the interposer, there are new opportunities to exploit it and provide other system benefits. We consider how the routing resources afforded by the interposer can be used to improve the network-on-chip's (NoC) capabilities and use the interposer to "disintegrate" a multi-core chip into smaller chips that individually and collectively cost less to manufacture than a large monolithic chip. However, distributing a system across many pieces of silicon causes the overall NoC to become fragmented, thereby decreasing performance as core-to-core communications between different chips must now be routed through the interposer. We study the performance-cost trade-offs of implementing an interposer-based, multi-chip, multi-core system and propose new interposer NoC organizations to mitigate the performance challenges while preserving the cost benefits.ii Acknowledgements First, I would like to express my sincerest gratitude to my supervisor, Natalie Enright Jerger, for her guidance and motivation during my time here. I have learned a lot from her expertise in computer architecture, on-chip networks, and research methodologies. I have been very lucky in having her as my mentor and she has been just wonderful to work with.I would also like to thank Gabriel Loh at AMD Corp., for his numerous inputs, suggestions and guidance throughout the work that I have been a part of during my programme. It has been a great opportunity and learning experience to have worked with him.

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“…We then tested out designs using SynFull [5] workloads. Finally, we looked at Full-System simulations using a cycle-accurate multi-core processor simulator.…”

Section: Methodsmentioning

confidence: 99%

“…To implement the NoC on an active interposer 6 , we simply place both the NoC links (wires) and the routers (transistors) on 5 This discussion treats diagonal links as y-dimension links. For the Folded Torus, bubble flow control must be applied in both dimensions.…”

Section: Physical Implementationmentioning

confidence: 99%

Enabling interposer-based disintegration of multi-core processors

Kannan

Jerger

Loh

2015

Proceedings of the 48th International Symposium on Microarchitecture

Self Cite

123

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“…Due to the exorbitant run-times required to simulate a 64-core system with a large NoC (88 nodes for CMesh and DB, 136 nodes for Mesh), we focus our experimental analysis on the workloads presented in Table II. To further verify the results using application behavior, we run multi-programmed SynFull [3] traffic patterns. We simulate a 4-way multitprogrammed mix of 16-way multi-threaded applications.…”

Section: Methodsmentioning

confidence: 99%

“…DB sees a modest performance degradation for Bisection; the static routing policy is not able to fully distribute the load in this pattern. 3 UpperLeft and Corners produce hotspots in the network that can lead to greater unfairness. We see the worst absolute performance for the UpperLeft traffic pattern across all topologies; DB is able to better distribute the hotspot loads and does not suffer as much as the other topologies.…”

Section: B Non-uniform Workloadsmentioning

confidence: 99%

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NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?

Jerger

Kannan

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Silicon interposer technology ("2.5D" stacking) enables the integration of multiple memory stacks with a processor chip, thereby greatly increasing in-package memory capacity while largely avoiding the thermal challenges of 3D stacking DRAM on the processor. Systems employing interposers for memory integration use the interposer to provide point-to-point interconnects between chips. However, these interconnects only utilize a fraction of the interposer's overall routing capacity, and in this work we explore how to take advantage of this otherwise unused resource.We describe a general approach for extending the architecture of a network-on-chip (NoC) to better exploit the additional routing resources of the silicon interposer. We propose an asymmetric organization that distributes the NoC across both a multi-core chip and the interposer, where each sub-network is different from the other in terms of the traffic types, topologies, the use or non-use of concentration, direct vs. indirect network organizations, and other network attributes. Through experimental evaluation, we show that exploiting the otherwise unutilized routing resources of the interposer can lead to significantly better performance.

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A scalable synthetic traffic model of Graph500 for computer networks analysis

Fuentes

Benito

Vallejo

et al. 2017

Concurrency and Computation

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SUMMARYThe Graph500 benchmark attempts to steer the design of High-Performance Computing systems to maximize the performance under memory-constricted application workloads. A realistic simulation of such benchmarks for architectural research is challenging due to size and detail limitations. By contrast, synthetic traffic workloads constitute one of the least resource-consuming methods to evaluate the performance. In this work, we provide a simulation tool for network architects that need to evaluate the suitability of their interconnect for BigData applications. Our development is a low computation-and memory-demanding synthetic traffic model that emulates the behavior of the Graph500 communications, and is publicly available in an open-source network simulator. The characterization of network traffic is inferred from a profile of several executions of the benchmark with different input parameters. We verify the validity of the equations in our model against an execution of the benchmark with a different set of parameters. Furthermore, we identify the impact of the node computation capabilities and network characteristics in the execution time of the model in a Dragonfly network.

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SynFull: Synthetic traffic models capturing cache coherent behaviour

Cited by 31 publications

References 42 publications

Enabling interposer-based disintegration of multi-core processors

Enabling interposer-based disintegration of multi-core processors

NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?

A scalable synthetic traffic model of Graph500 for computer networks analysis

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