Synchronous-mode evaluation of delays in CMOS structures

Delay modelling improvement for low voltage applications

“…As given in [6,7], this average current can be evaluated easily through effective parameters. This results in explicit equations for delays such as:…”

“…15), µ eff (equ. 7,8)and τ st and R(µ) (equ. 6), is quite good and validates the low voltage corrections proposed here.…”

“…In former work [6,7] we defined step responses of inverters (gates) as the average charge transfer necessary to equilibrate the output load under the input drive. This charge transfer has been understood as produced by the unbalance current developed in the cell under consideration, as:…”

“…for the fall (rise) time of an inverter (i), controlled by the preceding (i-1) th , where S subscript specifies step responses which model input, output slopes [6,7]. A and B coefficients, previously defined, represent the fraction of input ramp necessary to switch off N or P transistor block.…”

A new and accurate interconnection delay time evaluation in a general tree-type network

“…For our purposes, only the delay values are of interest, not the detailed waveforms. It has been generally recognize that, in CMOS structures, delay of gates can be accurately described through design parameters such as : technology, size of active components and parasitic capacitances [13,14]. We propose to extend this approach to resistive loading terms in order to accurately characterize interconnection delays, differentiating purely capacitive from mixed resistive and capacitive contributions.…”