Synchronous clocking schemes for large VLSI systems

Abstract

Recently a novel clock distribution scheme called Branch-and-Combine(BaC) has been proposed. The scheme guarantees constant skew bound irrespective of the size of the clocked network. It utilizes simple nodes to process clock signals. The paper uses a VLSI model to compare the properties of the new scheme to those of the well established H-Tree approach. Our study considers clocking 2-D processor meshes of arbitrary sizes. We evaluate and compare the relevant parameters of both schemes in a VLSI layout context. We show that for each BaC network, there is a certain threshold size after which it outperforms the corresponding tree network. We utilize parameters such as clock skew, link costs, node costs and area efJiciency as the basis for comparison.