Synchronization verification in system-level design with ILP solvers

Sakunkonchak, Thanyapat; Komatsu, Setsuko; Fujita, Masahiro

doi:10.1109/memcod.2005.1487902

Cited by 6 publications

(6 citation statements)

References 31 publications

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“…With the objective function and the 9 constraints, we can use sophisticated ILP solvers, such as PULP [25], to obtain one scheduling solution. Then, the new DDG could be easily generated by adding extra nodes or edges according to the values of the binary variables.…”

Section: B Mapping Flexibility Evaluationmentioning

confidence: 99%

Routability-Enhanced Scheduling for Application Mapping on CGRAs

Zeng

Wang

2021

IEEE Access

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Coarse-Grained Reconfigurable Architectures (CGRAs) are a promising solution to domainspecific applications for their energy efficiency and flexibility. To improve performance on CGRA, modulo scheduling is commonly adopted on Data Dependence Graph (DDG) of loops by minimizing the Initiation Interval (II) between adjacent loop iterations. The mapping process usually consists of scheduling and placement-and-routing (P&R). As existing approaches don't fully and globally explore the routing strategies of the long dependencies in a DDG at the scheduling stage, the following P&R is prone to failure leading to performance loss. To this end, this paper proposes a routability-enhanced scheduling for CGRA mapping using Integer Linear Programming (ILP) formulation, where a global optimized scheduling could be found to improve the success rate of P&R. Experimental results show that our approach achieves 1.12× and 1.22× performance speedup, 28.7% and 50.2% compilation time reduction, as compared to 2 state-of-theart heuristics.INDEX TERMS Coarse-grained reconfigurable architectures (CGRAs), modulo scheduling, routing strategy, placement and routing (P&R)

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Section: B Mapping Flexibility Evaluationmentioning

confidence: 99%

Routability-Enhanced Scheduling for Application Mapping on CGRAs

Zeng

Wang

2021

IEEE Access

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“…This section describes our method to dynamically analyze concurrent behaviors or so called synchronization verification [13]. In system-level design languages such as SpecC, extra constructs are added to C in order to describe the characteristics of hardware.…”

Section: Verification With Symbolic Simulation-based Reasoningmentioning

confidence: 99%

“…A complete discussion of abstraction refinement for model checking is beyond the scope of this paper. The interested reader is directed to [14,13] for a detailed treatment of this subject. Figure 8 shows a simple example that illustrates the use of CEGAR and ILP solver for synchronization verification.…”

Section: Synchronization Verificationmentioning

confidence: 99%

“…In this case there is a conflict in the formulae and a deadlock occurs due to the wait e1 and wait e2 are executing prior to notify e1 and notify e2, respectively. The detailed algorithm and explanation of synchronization verification can be found in [13]. Several experiments were conducted on a Pentium4 2.8-GHz machine with 2 GB of RAM running Linux.…”

Section: Synchronization Verificationmentioning

confidence: 99%

“…In this paper, we describe the methods for the verification and synthesis for systemlevel designs that were published by the authors [3] [13] [15] [11]. The first method is based on traversals of SDGs and mainly checks static aspects of the design descriptions.…”

Section: Introductionmentioning

confidence: 99%

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Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation

Fujita

Seto

Sakunkonchak

2008

SAT

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Program slicing is a software-analysis technique that generates System Dependence Graphs (SDGs) by which dependencies among program statements can be identified through their traversal. We have developed a program slicing tool for SpecC, a C-based system level design language for hardware/software co-designs, on top of a program slicer for C/C++. This program slicing tool can generate SDGs from any combined descriptions in C, C++, and SpecC, and can be used to analyze design descriptions for hardware/software co-designs uniformly and smoothly in all the combined descriptions. In this paper, after reviewing our program slicer that generates SDGs, we present verification and synthesis techniques for hardware/software co-designs through various analyses on SDGs and generations of SAT/ILP problems from them. For analysis and verification of the combined descriptions, we examine SDGs statically by traversing them with SAT/ILP solvers as verification engines. With this method, many static checks can be efficiently realized even if the target design descriptions are fairly large. We first present techniques for checking synchronization among concurrent processes described in SpecC through symbolic analysis on SDGs. The techniques could verify the synchronization of MPEG4 descriptions with about 48,000 lines within 10 seconds. The techniques can be applied to automatic conversions between sequential and parallel computations. One such application to automatic program serialization is presented. By using the technique for automatic program serialization, we could serialize Vocoder descriptions with about 10,000 lines in around 1 minute. As for synthesis from the combined descriptions, we present an optimal code generation method based on SAT formulation. It can generate codes for reconfigurable processors with minimum code lengths. The sizes of problems as SAT formulation range from 10,000 to 100,000 variables and 100,000 to 500,000 clauses for the largest configurations. With appropriate uses of the state-of-the-art SAT solvers and related tools, we show that fairly practical sizes of verification and synthesis problems can be solved by analyzing SDGs generated from the combined descriptions.

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Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction

Sakunkonchak

Komatsu

Fujita

Automated Technology for Verification and Analysis

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Abstract. Due to the success of the model checking technique in the hardware domain, over the last few years, model checking methods have been applied to the software domain which poses its own challenges, as software tends to be less structured than hardware. Predicate abstraction is widely applied to reduce the state-space by mapping an infinite state-space program to an abstract program of Boolean type. The cost for computation of abstraction and model checking depends on the number of state variables in the abstract model. In this paper, we propose a simple, yet efficient method to minimize the number of predicates for predicate abstraction. Given a spurious counterexample, at least one predicate is assigned at each program location during the refinement process. The computational cost depends proportionally to the number of assigned predicates. In this paper, instead, we search the counterexample to find the conflict predicates that caused this counterexample to be spurious. Then, we assign the necessary predicates to the abstract model. We compare the performance of our technique with the interpolation-based predicate abstraction tool like BLAST. The proposed method presents significantly better experimental results on some examples with large set of predicates.

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Synchronization verification in system-level design with ILP solvers

Abstract: Concurrency is one of the most important issues in

Cited by 6 publications

References 31 publications

Routability-Enhanced Scheduling for Application Mapping on CGRAs

Routability-Enhanced Scheduling for Application Mapping on CGRAs

Dependence Graph Based Verification and Synthesis of Hardware/Software Co-Designs with SAT Related Formulation

Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction

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