Synaptic plasticity in spiking neural networks (SP/sup 2/INN): a system approach

Mehrtash, N.; Jung, D.; Hellmich, H. H.; Schoenauer, T.; Lu, V.T.; Klär, H.

doi:10.1109/tnn.2003.816060

Cited by 40 publications

(17 citation statements)

References 22 publications

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“…In the "neuromorphic" approach [20], chips use analogue circuitry to emulate as closely as possible the actual biophysics of real neurons [60]. The "neuroprocessor" approach [35], by contrast, attempts to use general-purpose digital components with an internal structure optimised for massively parallel neural processing. Each has its limitations: neuromorphic chips are power-and component-efficient, but relatively small-scale, and have limited or fixed model support.…”

Section: Dedicated Neural Hardwarementioning

confidence: 99%

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System

Rast

Navaridas

Jin

et al. 2011

Int J Parallel Prog

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Neural networks present a fundamentally different model of computation from the conventional sequential digital model, for which conventional hardware is typically poorly matched. However, a combination of model and scalability limitations has meant that neither dedicated neural chips nor FPGA's have offered an entirely satisfactory solution. SpiNNaker introduces a different approach, the "neuromimetic" architecture, that maintains the neural optimisation of dedicated chips while offering FPGA-like universal configurability. This parallel multiprocessor employs an asynchronous event-driven model that uses interrupt-generating dedicated hardware on the chip to support real-time neural simulation. Nonetheless, event handling, particularly packet servicing, requires careful and innovative design in order to avoid local processor congestion and possible deadlock. We explore the impact that spatial locality, temporal causality and burstiness of traffic have on network performance, using tunable, biologically similar synthetic traffic patterns. Having established the viability of the system for real-time operation, we use two exemplar neural models to illustrate how to implement efficient event-handling service routines that mitigate the problem of burstiness in the traffic. Extending work published in ACM Computing Frontiers 2010 with on-chip testing, simulation results indicate the viability of SpiNNaker for large-scale neural modelling, while emphasizing the need for effective burst management and network mapping. Ultimately, the goal is the creation of a library-based development system that can translate a high-level neural model from any description 123Int J Parallel Prog environment into an efficient SpiNNaker instantiation. The complete system represents a general-purpose platform that can generate an arbitrary neural network and run it with hardware speed and scale.

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Section: Dedicated Neural Hardwarementioning

confidence: 99%

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System

Rast

Navaridas

Jin

et al. 2011

Int J Parallel Prog

View full text Add to dashboard Cite

show abstract

“…The second method is the "neural accelerator", relying on carefully optimised digital technologies with shared synaptic memory. MASPINN [6] and SP 2 INN [7] are examples of this approach. In principle digital devices are programmable and thus more flexible than analogue, however, to date, the need to use bit-mapped inputs over standard bus interfaces for synaptic memory access limits model choice.…”

Section: How To Map Neural Network To Hardware?mentioning

confidence: 99%

Virtual synaptic interconnect using an asynchronous network-on-chip

Rast

Yang

Khan

et al. 2008

2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence)

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Abstract-Given the limited current understanding of the neural model of computation, hardware neural network architectures that impose a specific relationship between physical connectivity and model topology are likely to be overly restrictive. Here we introduce, in the SpiNNaker chip, an alternative approach: a mappable virtual topology using an asynchronous network-on-chip (NoC) that decouples the "logical" connectivity map from the physical wiring. Borrowing the established digital RAM model for synapses, we develop a concurrent memory access channel optimised for neural processing that allows each processing node to perform its own synaptic updates as if the synapses were local to the node. The highly concurrent nature of interconnect access, however, requires careful design of intermediate buffering and arbitration. We show here how a locally buffered, one-transaction-per-node model with multiple synapse updates per transaction enables the local node to offload continuous burst traffic from the NoC, allowing for a hardware-efficient design that supports biologically realistic speeds. The design not only presents a flexible model for neural connectivity but also suggests an ideal form for general-purpose high-performance on-chip interconnect. I. HOW TO MAP NEURAL NETWORKS TO HARDWARE?W HILE the dynamics of spiking neural networks at the neuron level are fairly well-understood, questions of network organisation at the functional unit level, data representation, and inter-system communication remain largely unanswered [1]. Important biological discoveries [2] have fuelled ongoing debates on the nature of neural structure and dynamics [3], which seem unlikely to lead to any resolution without powerful and sophisticated modelling probably incorporating dedicated hardware [4]. How to implement this hardware, however, is an almost equally contentious question.One popular method is the "neuromorphic" chip, exemplified by [5], using analogue circuits to model neural properties directly. While these devices remain an important research area since analogue circuits are in principle more biologically accurate as well as more space-efficient, in practice analogue circuitry suffers from a significant device and process technology lag behind digital. The second method is the "neural accelerator", relying on carefully optimised digital technologies with shared synaptic memory. MASPINN [6] and SP 2 INN [7] are examples of this approach. In principle digital devices are programmable and thus more flexible than analogue, however, to date, the need to use bit-mapped inputs over standard bus interfaces for synaptic memory access limits model choice. Historically, both models, relying on a direct mapping from the hardware to the physical structure More recently, FPGA's [8] offer the possibility for configurable topologies and processing functions, but use a circuit-switched connectivity model that severely constrains utilisation of routing resources. If the mapping of the neural model to the FPGA remains one-to-one, then, just...

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“…The four right pictures in Fig. 4 show the network activity in time slices 10K+ (2,3,4,5). Where K=1, 2, 3, .…”

Section: Image Preprocessing With Dynamic Synapsesmentioning

confidence: 99%

Image preprocessing with dynamic synapses

Mehrtash

Jung

Klär

2003

Neural Computing & Applications

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Different algorithms suitable for a specific class of picture were developed for image processing. We will represent the filtering capability of a spiking neural network based on dynamic synapses. For this intention we chose an x-ray image of the human coronary trees and another noisy image. In other words the task at hand is to show how accurately such a network is able to store various aspects (object/background) of stimulus in the variables which describe dynamic of synaptic response. The behavior of these synapses influences the effective connection in the network in a short time-scale. Such a network has a low activity and a balanced behavior. Dynamic synapses are able to adjust their behavior by fast changing stimuli. These synapses retain the information in the variables, such as potential and time.

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Synaptic plasticity in spiking neural networks (SP/sup 2/INN): a system approach

Cited by 40 publications

References 22 publications

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System

Virtual synaptic interconnect using an asynchronous network-on-chip

Image preprocessing with dynamic synapses

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