Symmetrical SOI MESFET with a dual cavity region (DCR-SOI MESFET) to promote high-voltage and radio-frequency performances

Anvarifard, Mohammad K.

doi:10.1016/j.spmi.2016.09.003

Cited by 13 publications

(1 citation statement)

References 22 publications

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“…Many researchers have been proposed various SOI MOSFET formations to suppress SCEs and their related complications. [6][7][8][9][10][11][12][13] The presence of source-drain junctions on both sides of the channel remains a significant issue in SOI and FETs devices, and junctionless transistors have been suggested as a solution. [14,15] Several articles on junctionless FET (JLFET) have been presented to enhance their performance.…”

Section: Introductionmentioning

confidence: 99%

Stacked Single‐Gate Silicon on Insulator 4H‐SiC Junctionless Field‐Effect Transistor with a Buried P‐Type 4H‐SiC Layer

Madadi

Orouji

2022

Physica Status Solidi (a)

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This study describes a single‐gate silicon on insulator junctionless metal–oxide–semiconductor field‐effect transistor (SJL‐MOSFET) with inserted buried 4H‐SiC p‐type layer (B‐SJL‐MOSFET). The embedded p‐type layer is placed at the bottom of the active regions, achieving the full depletion of the channel in the off‐state mode. The p‐type layer affects the depletion region of the channel, which helps us have a full depletion area with a lower gate electrode work function. The main reason for using SiC material instead of silicon is the higher electrostatic integrity and a shorter natural length than silicon, resulting in a better short channel effect (SCE). In addition, the high‐k oxide is stacked for achieving lower natural length and better subthreshold swing (SS). The p‐type layer improves the leakage current (Ioff) by ≈105 in the event that it slightly diminishes the on‐state current (Ion) and improves the SS. Improvement of off‐current is due to higher barriers between source‐channel side and reduces the parasitic BJT in the off‐mode.

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