Symbolic Model Checking

McMillan, Kenneth L.

doi:10.1007/978-1-4615-3190-6_3

Cited by 631 publications

(722 citation statements)

References 2 publications

Supporting

Mentioning

718

Contrasting

Unclassified

Order By: Relevance

“…Using this framework, we verified an ATM switch fabric from Nortel Networks, which cannot be verified by plain model checking due to state space explosion. Here, we use VIS as target model checker, however, we can still use some other alternatives, such as SMV [13]. Through out the verification, we found bugs in the design, which were not caught through simulation.…”

Section: Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Compositional Verification of a Switch Fabric from Nortel Networks

Peng

Tahar

Mokhtari

2003

Formal Methods and Software Engineering

View full text Add to dashboard Cite

With the development of ASIC designs, simulation cannot cover all the corner cases in a complicated design. Model checking is a fully automatic approach to verify a finite state machine against its temporal specifications. However, its application is limited by the size of the system to be verified. Compositional verification and model reduction are two possible methods to tackle this problem. In this paper, we propose a verification framework based on assumeguarantee compositional model checking, where we can apply model checking to do exhaustive verification at the module level and conduct global properties via compositional reasoning. In this framework, temporal specifications are synthesized into Verilog modules. In case a module under verification is beyond the capability of model checking, the proposed model reduction algorithm is used. We implemented the framework on top of the VIS tool and applied it on an ATM switch fabric from Nortel Networks.

show abstract

Section: Resultsmentioning

confidence: 99%

“…However, its application is limited by the size of the system to be verified. Current model checking tools [2,13,3] are limited to several hundred Boolean state variables due to state space explosion. There are two main methods to tackle this problem: compositional verification and model reduction.…”

Section: Introductionmentioning

confidence: 99%

Compositional Verification of a Switch Fabric from Nortel Networks

Peng

Tahar

Mokhtari

2003

Formal Methods and Software Engineering

View full text Add to dashboard Cite

show abstract

“…(However, many of the analyses were intractable without the optimizations explained in Sections 4 and 5.) We used and modified CMU's BDD-based model checker SMV [13] release 2.4.4 in our studies.…”

Section: Case Studiesmentioning

confidence: 99%

Optimizing symbolic model checking for statecharts

Chan

Anderson

Beame

et al. 2001

IIEEE Trans. Software Eng.

View full text Add to dashboard Cite

AbstractÐSymbolic model checking based on binary decision diagrams is a powerful formal verification technique for reactive systems. In this paper, we present various optimizations for improving the time and space efficiency of symbolic model checking for systems specified as statecharts. We used these techniques in our analyses of the models of a collision avoidance system and a faulttolerant electrical power distribution (EPD) system, both used on commercial aircraft. The techniques together reduce the time and space requirements by orders of magnitude, making feasible some analysis that was previously intractable. We also elaborate on the results of verifying the EPD model. The analysis disclosed subtle modeling and logical flaws not found by simulation.

show abstract

“…First, counter-examples are restricted to universally-quantified formulas, and second, counterexamples have been viewed as infinite or finite paths, starting from the initial state, that illustrate failure of a given property. This notion of path-like counter-examples has been implemented in SMV [McM93,CGMZ95]. Yet only a subset of universally-quantified CTL (ACTL), namely ACTL ∩ LTL, has linear counter-examples [CLJV02].…”

Section: Introductionmentioning

confidence: 99%

Proof-Like Counter-Examples

Gurfinkel

Chećhik

2003

Tools and Algorithms for the Construction and Analysis of Systems

View full text Add to dashboard Cite

Abstract. Counter-examples explain why a desired temporal logic property fails to hold, and as such considered to be the most useful form of output from modelcheckers. Reported explanations are typically short and described in terms of states and transitions of the model; as a result, they can be effectively used for debugging. However, counter-examples are not available for every CTL property and are often inadequate for explaining exactly what the answer means [CLJV02]. In this paper, we present the approach of annotating counter-examples with additional proof steps. This approach does not sacrifice any of the advantages of traditional counter-examples, yet allows the user to understand and navigate through the counter-example better. We describe our proof system, discuss how to connect it with counter-example generators, and present KEGVis -a tool for visualizing and browsing the annotated counter-examples.

show abstract

Symbolic Model Checking

Cited by 631 publications

References 2 publications

Compositional Verification of a Switch Fabric from Nortel Networks

Compositional Verification of a Switch Fabric from Nortel Networks

Optimizing symbolic model checking for statecharts

Proof-Like Counter-Examples

Contact Info

Product

Resources

About