Symbol-Decision Successive Cancellation List Decoder for Polar Codes

Abstract

Abstract-Polar codes are of great interests because they provably achieve the capacity of both discrete and continuous memoryless channels while having an explicit construction. Most existing decoding algorithms of polar codes are based on bit-wise hard or soft decisions. In this paper, we propose symbol-decision successive cancellation (SC) and successive cancellation list (SCL) decoders for polar codes, which use symbol-wise hard or soft decisions for higher throughput or better error performance. First, we propose to use a recursive channel combination to calculate symbol-wise channel transition probabilities, which lead to symbol decisions. Our proposed recursive channel combination also has a lower complexity than simply combining bit-wise channel transition probabilities. The similarity between our proposed method and Arikan's channel transformations also helps to share hardware resources between calculating bit-and symbol-wise channel transition probabilities. Second, a two-stage list pruning network is proposed to provide a trade-off between the error performance and the complexity of the symbol-decision SCL decoder. Third, since memory is a significant part of SCL decoders, we propose a pre-computation memory-saving technique to reduce memory requirement of an SCL decoder. Finally, to evaluate the throughput advantage of our symbol-decision decoders, we design an architecture based on a semi-parallel successive cancellation list decoder. In this architecture, different symbol sizes, sorting implementations, and message scheduling schemes are considered. Our synthesis results show that in terms of area efficiency, our symbol-decision SCL decoders outperform both bit-and symbol-decision SCL decoders.

Performance Bounds of Concatenated Polar Coding Schemes

“…Various architectures have been considered for parallel efficient implementation of SC and list SC decoding with improved throughput, e.g. [3], [4], [5], [6]. Those architectures involve decomposing the overall polar code into an inner code and an outer code, and using SC to decode the inner code and maximum-likelihood (ML) to decode the outer code.…”

Fast and Flexible Successive-Cancellation List Decoders for Polar Codes

“…The symbol-decision SCL decoder architecture of [12] shows lower area occupation than the design in this paper for L = 4 but it comes at the cost of lower throughput and higher latency. Our decoder architecture achieves 192% higher throughput and 66% lower latency than [12] which resulted in 17% higher area efficiency.…”

“…Our decoder architecture achieves 192% higher throughput and 66% lower latency than [12] which resulted in 17% higher area efficiency.…”

“…a bit estimation or an LLR value update), and might thus last a different number of clock cycles. A group of M bits were allowed to be decoded together in [11], [12]. [13] proposed a high throughput architecture based on a tree-pruning scheme and further extended it to a multimode decoder in [14].…”

On Path Memory in List Successive Cancellation Decoder of Polar Codes

“…The hardware architecture of LSCD [5]- [10] implements L SCD kernels to support the parallel calculations of L paths, indicating the hardware complexity is at least L times that of the single SCD. To achieve a moderate hardware complexity, the semi-parallel architecture [11] and the folded partial-sum network (PSN) [12] originally proposed for a single SCD are also adopted in the LSCD architecture [5]- [9] due to their low complexity. Several L × L crossbars are used for the permutations of log-likelihood ratios (LLRs), partial-sums and partial decoded vectors among different memories according to the results of list management.…”