Switching loss optimisation of cascaded H-bridge converters for bidirectional grid-tie battery energy storage systems

Abstract

Abstract-Multilevel converters are an emerging industrial technology and are the subject of a substantial amount of research. However, they are yet to find their way into many mainstream engineering applications. This paper presents a method of quantifying the benefits and disadvantages of multilevel converters of increasing order. The analysis focuses on the cascaded H-bride topology for grid-tie battery inverter applications. The analysis includes both semiconductors losses and semiconductor driver losses. It is shown that multilevel converters can have significant benefits over their conventional counterparts, but that more levels is not necessarily better. This paper's important result is to create a quantitative measure of the pros and cons of multilevel architecture.

On the impact of current generation commercial gallium nitride power transistors on power converter loss

“…As the number of cascaded H‐bridges increases, there are more switching devices required, but they can have a lower voltage rating. In an effort to investigate the optimum number of cascaded levels, total switching device associated power loss was calculated from a range of sources: on‐state resistance, transient gate dissipation, V DS I D transient product during switching and gate driver losses [4].…”

A software-based method for energy losses decreasing in cascaded buck + boost DC-DC converter

“…They arise when switch switches from the nonconducting to conducting state and vice versa. The value of these losses for switch based on MOSFET transistors depends on the drain-source voltage, the current through the conducting channel, and the switching duration [1].…”

“…For DC power supply systems, a buck + boost converter topology is considered promising [1,3]. The power circuit diagram of such a converter is shown in figure 1.…”

“…The absolute value of the inductor negative inductor offset current depends on the performance of the converter. In [2], a formula was proposed for calculating its minimum necessary and sufficient value from the condition that the energy stored by the inductor is sufficient to recharge the capacitances and subsequently unblock the antiparallel diode of the corresponding transistor: (1) where and are the maximum voltage amplitudes on sides 1 and 2 of the converter, respectively, is the inductance, is the total capacitance of the parasitic capacitors of the switched half-bridge.…”

An Experimental Investigation of MOSFET Intrisic Body Diode Performance

“…An example of a situation in which this would be of great use is the optimisation of the design of N th order multilevel converters, as in [7], where one is less interested in what the performance of specific device is but instead what the performance of a device with given properties is likely to be.…”