Switching activity estimation using limited depth reconvergent path analysis

Abstract

We describe a method of polynomial simulation to calculate switching activities in a general-delay combinational logic circuit. This method is a generalization of the exact signal probability evaluation method due to Parker and McCluskey, which as been extended to handle temporal correlation and arbitrary transport delays.Our method is parameterized by a single parameter 1, which determines the speed-accuracy tradeoff. 1 indicates the depth in terms of logic levels over which spatial signal correlation is taken into account. This is done by only taking into account reconvergentpaths whose length is at most 1. The rationale is that ignoring spatial correlation for signals that reconverge after many levels of logic introduces negligible error.We present results that show that the error in the switching activity and power estimates is very small even for small values of 1. In fact, for most of the examples we tried, power estimates withl= 1 are within 5% of the exact. However, this error can be higher than 20 % for some examples. More robust estimates are obtained with I= 2, providing a good compromise between speed and accuracy.

Power Estimation Using Probability Polynomials

“…It has been our experience that dominators (and consequently super-gates) are not very common in a general logic circuit [5]. In most circuits, due to a high degree of reconvergent paths, dominators of primary inputs exist only close to the primary outputs.…”

“…We describe a method of polynomial simulation to calculate switching activities in a general-delay logic circuit [5] which has been extended to handle sequential circuits. This method is a generalization of the exact signal probability evaluation method due to Parker and McCluskey [18], which has been extended to handle temporal correlation and arbitrary transport delays.…”

Analysis of voltage overscaled computer arithmetics in low power signal processing systems

“…Readers are referred to [12]- [15] for existing work on switching activity estimation. In this paper, we mainly use the approach addressed in [12], [14] to calculate these transition probabilities.…”

Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation

“…Both simulation-based (e.g., [3]) and probabilistic (e.g., [7]) techniques have been proposed for the computation of . Simulation-based techniques use a logic or timing simulator.…”

“…The columns labeled incompletely specified indicate the power savings from exploiting the don't cares in incompletely specified test patterns over an already ordered sequence of completely specified test patterns. In all cases a power estimator tool integrated in SIS was used for estimating the actual power dissipation from applying the test sequences [7]. As can be readily concluded, large power savings ranging from 30% to 60% are achieved in most cases.…”