Switched Capacitor Variable Delay Line

Ramazanoglu, Semih; Batur, Okan Zafer

doi:10.1109/iscas.2018.8351457

Cited by 3 publications

(2 citation statements)

References 12 publications

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“…In addition to some necessary components, a low-cost TX I/Q imbalance compensation block and a low-cost I/Q imbalance estimation block were integrated into the digital front end. Furthermore, a squaring circuit and a variable-delay line (VDL) were integrated into the analog domain [25,26].…”

Section: I/q Imbalance Calibration Schemementioning

confidence: 99%

A Hybrid Scheme for TX I/Q Imbalance Self-Calibration in a Direct-Conversion Transceiver

Wang,

Gao,

Liu

et al. 2024

Electronics

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A generic transmitter (TX) I/Q imbalance self-calibration method, which was designed based on a hybrid analog and digital structure, is proposed in this paper. The whole calibration scheme was implemented using low-complexity digital–analog circuits based on a zero-force feedback loop. In order to eliminate the negative effect of local oscillator (LO) harmonics on the calibration, we used a variable-delay line (VDL) in the analog domain instead of the digital phase compensator. The prototype chip was fabricated within a 0.2∼5.0 GHz direct-conversion transmitter in a 65 nm CMOS process, and measurements found an image rejection ratio (IRR) of 65 dBc.

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Section: I/q Imbalance Calibration Schemementioning

confidence: 99%

A Hybrid Scheme for TX I/Q Imbalance Self-Calibration in a Direct-Conversion Transceiver

Wang,

Gao,

Liu

et al. 2024

Electronics

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“…There are several ways to implement a digitally controlled variable delay cell. The popular method is a delay cell with shunt capacitors [8]. Assuming that the delay cell is a first-order RC circuit, this delay cell adjusts the capacitance depending on the digital input patterns.…”

Section: Introductionmentioning

confidence: 99%

A 13-bit 3-MS/s Asynchronous SAR ADC with a Passive Resistor Based Loop Delay Circuit

Lee

2019

Electronics

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An asynchronous successive approximation register (SAR) ADC incorporates a passive resistor based delay cell to reduce power consumption and accommodate the SAR ADC with a reconfigurable sampling frequency or tapered bit period without repeated delay calibration. The ADC aims to have a sampling frequency of several MS/s. The proposed delay cell adopts resistance controlled delay architecture to generate a delay of nanoseconds with high linearity. The resistance controlled delay cell is based on a passive resistor instead of a MOS transistor using a triode region to avoid the nonlinear delay characteristic of active devices. From the analysis of the linearity of delay cell, the passive resistor based delay cell achieves a delay error of about 5 percent. The prototype ADC to validate the proposed passive resistor based delay cell is fabricated in 40 nm CMOS. The ADC occupies 0.054 mm2 and achieves an SNDR of 57.4 dB under 67 μW power dissipation at a 1.1 V supply with a 3 MHz sampling frequency.

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