2015 IEEE International Symposium on Circuits and Systems (ISCAS) 2015
DOI: 10.1109/iscas.2015.7168904
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Switched capacitor quasi-adiabatic clocks

Abstract: Abstract-Clock Distribution Networks (CDNs) in high speed designs can consume 30-50% of the total chip dynamic power. Adiabatic clock circuits can save some of this power, but these depend on a time varying power supply which is difficult to implement in practice. In this paper, we present the first quasiadiabatic clock circuit with a constant supply voltage at high speeds. Our proposed adiabatic clocks attain an average 23% clock power savings with better slew rate and the same skew compared to traditional bu… Show more

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Cited by 1 publication
(3 citation statements)
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“…The skew reduction methodology, described in Chapter 5, explains the inductor Fig. 2 Energy recycling techniques include (a) Quasi-adiabatic clocking topology places a capacitor in parallel with clock load to store energy [13] (b) Parallel resonance topology places an inductor in parallel with clock load [40] (c) Series resonance topology places an inductor in the discharge path of clock load [2] (d) Quasi-resonant clocking topology places an inductor and an additional transistor to conditionally disconnect the inductor [42].…”
Section: Main Contributionsmentioning
confidence: 99%
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“…The skew reduction methodology, described in Chapter 5, explains the inductor Fig. 2 Energy recycling techniques include (a) Quasi-adiabatic clocking topology places a capacitor in parallel with clock load to store energy [13] (b) Parallel resonance topology places an inductor in parallel with clock load [40] (c) Series resonance topology places an inductor in the discharge path of clock load [2] (d) Quasi-resonant clocking topology places an inductor and an additional transistor to conditionally disconnect the inductor [42].…”
Section: Main Contributionsmentioning
confidence: 99%
“…If C adiabatic is not disconnected during some portions of the cycle, the clock buffer will have to charge/discharge the total capacitive load C load + C adiabatic each cycle which would increase the overall power consumption to (C load + C adiabatic )V 2 dd f . The quasi-adiabatic clocking employs a pass gate that would disconnect the C adiabatic capacitor, depending upon control signals that determine the duration of the energy recovery and reuse states [13].…”
Section: Energy Recycling Techniquesmentioning
confidence: 99%
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