Switched-capacitor integrators with low finite-gain sensitivity

Haug, K.; Maloberti, Franco; Temes, Gábor C.

doi:10.1049/el:19850818

Cited by 74 publications

(22 citation statements)

References 4 publications

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“…From simulations, to keep the overall INL error to be less than a quarter of an LSB, will require the following minimum gain for the integrator amplifier, Despite the low frequency of operation, for high performance exceptionally high gain values are needed, but which are typically unobtainable. This problem can be partially solved through the use of finite-gain insensitive integrators [7][8][9]. It is envisaged that these types of integrators will be used in the ramp generators as part of a pipeline architecture, where two relaxation oscillators will be connected in series, they will each have 8 bits of resolution.…”

Section: Resultsmentioning

confidence: 99%

<title>Voltage to frequency converter for DAC test</title>

Hogan¹,

Farrell²

2005

SPIE Proceedings

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In this paper a modified relaxation oscillator is proposed as the core of an analog to digital modulator for on chip signal extraction for test. The architecture uses digital current source generation and digital switching in place of active circuitry. The resulting design allows for high input sensitivity, robustness to component variation while occupying little silicon area. This paper provides solutions on the main challenges in implementing this modulator and how it may be integrated with a digital based tester.

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Section: Resultsmentioning

confidence: 99%

<title>Voltage to frequency converter for DAC test</title>

Hogan¹,

Farrell²

2005

SPIE Proceedings

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“…• Auto-zero or correlated double sampling [30,31] • Chopper stabilization [32,33] The auto-zero or correlated double sampling technique reduces the offset and low-frequency noise at the system level. [34,35] This technique requires sampled data operation.…”

Section: 51voltage Outputmentioning

confidence: 99%

17 Interface Circuitry and Microsystems

Malcovati

Maloberti

2006

MEMS: A Practical Guide to Design, Analysis, and Applications

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“…This problem can be partially solved through the use of finite-gain insensitive integrators [7,9,10]. …”

Section: Finite Op-amp Gain Errormentioning

confidence: 99%

“…To achieve this the op-amp gain for the first stage will have to be 127dB as shown in Figure 10. As mentioned previously in section 3.2, through the use of finite-gain insensitive integrators [7,9,10] this minimum gain can be reduced.…”

Section: Example Pipeline Oscillatormentioning

confidence: 99%

A pipeline voltage-to-time converter for high resolution signal extraction off-chip

Hogan¹,

Farrell²

2005

5th IEE International Conference on ADDA 2005. Advanced a/D and D/a Conversion Techniques and Their Applications

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In this paper a pipelined voltage to time converter is presented. It is targeted at the extraction, in digital form, of sensitive analog signals from an integrated circuit. The tester is able to measure the period of this signal and derive the original voltage. The input signal is low frequency. This paper provides solutions to the main challenges in implementing this modulator and how it may be integrated with a digital tester.

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Switched-capacitor integrators with low finite-gain sensitivity

Cited by 74 publications

References 4 publications

<title>Voltage to frequency converter for DAC test</title>

<title>Voltage to frequency converter for DAC test</title>

17 Interface Circuitry and Microsystems

A pipeline voltage-to-time converter for high resolution signal extraction off-chip

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