SWARM: A Self-Organization Approach for Layout Automation in Analog IC Design

Marolt, Daniel; Scheible, Jürgen; Jerke, Goeran; Marolt, Vinko

doi:10.18178/ijeee.4.5.374-385

Cited by 11 publications

(3 citation statements)

References 32 publications

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“…The developed architecture offers an effective way to [30], Bayesian fusion [38], layout migration and reuse [61], layout self-organization [62], reinforcement learning [63], and training our deep neural network using a database of successfully fabricated circuits. However, the current cost of IC fabrication prevented us from creating such a database, given the number of end-to-end designs that must have been completed.…”

Section: Table VI To Tablementioning

confidence: 99%

Analog RF Circuit Sizing by a Cascade of Shallow Neural Networks

Beaulieu¹,

Dumesnil²,

Nabki³

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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A deep neural network architecture for the automatic sizing of analog circuit components is proposed, with a focus on radio frequency (RF) applications in the 2 to 5 GHz region. It addresses the challenges of the typically small number of examples for network training and the existence of multiple solutions, of which impractical values for integrated circuit implementation. We address these issues by restricting the learning to one component size at a time, thanks to a cascade of dedicated shallow neural networks (SNN), where each network constrains the prediction of the next ones. Moreover, the SNNs are individually tuned by a genetic algorithm for the prediction order and accuracy. This reduction of the solution space at each step allows the use of small training sets, and the introduced constraints between SNNs handle component interdependencies. The method is successfully validated on three different types of RF microcircuits: a low-noise amplifier (LNA), a voltage-controlled oscillator (VCO), and a mixer, using 180 nm and 130 nm CMOS implementations. All the predictions were within 5 % of the true values, both at the component and performance levels, and all the responses were obtained in less than 5 s, after 4 to 47 min. training on a regular PC station. The obtained results show that the proposed method is fast and applicable to arbitrary analog circuit topologies, with no need to retrain the developed neural network for each new set of desired circuit performances.

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Section: Table VI To Tablementioning

confidence: 99%

Analog RF Circuit Sizing by a Cascade of Shallow Neural Networks

Beaulieu¹,

Dumesnil²,

Nabki³

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…A recent placement approach utilizes swarm intelligence in order to arrange procedurally generated blocks [15]. Different hierarchy levels are used to encapsulate dedicated constructive tasks and to organize recursive placement cycles while considering constraints.…”

Section: A State Of the Artmentioning

confidence: 99%

“…A-B-C). Since in the example elemB must be placed last, the intended order has to be corrected either using further procedural code (which may again show problems) or by placement or correction algorithms (such as in [15,16], resp. ).…”

Section: B Layout Description Of Cs-dac Sub Blocksmentioning

confidence: 99%

MESH: Explicit and flexible generation of analog arrays

Prautsch

Eichler

Reich

et al. 2017

2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (

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Analog layout design is a costly and error-prone task since analog synthesis is still far from applicable. It is expected that procedural bottom-up generators managing constructive tasks will be part of future synthesis flows. Generators contain expert knowledge implicitly within complex and hard-to-understand source code. Due to a lack of explicit layout definition and uncaptured design intent, generator layouts can hardly be adapted by constructive algorithms directly. Thus, synthesis flows need to adapt layout blocks by varying generator parameters which results in computation-expensive optimization. This paper introduces MESH—a software structure to define detailed and flexible layout generators explicitly. Using MESH, just a few lines of code describe complex layouts while all relations and design intents, such as element positions and routing styles, are captured through abstract commands. As a result, generators are created fast with less programming errors, and constructive algorithms can modify the generator structure directly

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Special Layout Techniques for Analog IC Design

Lienig¹,

Scheible

2020

Fundamentals of Layout Design for Electronic Circuits

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SWARM: A Self-Organization Approach for Layout Automation in Analog IC Design

Cited by 11 publications

References 32 publications

Analog RF Circuit Sizing by a Cascade of Shallow Neural Networks

Analog RF Circuit Sizing by a Cascade of Shallow Neural Networks

MESH: Explicit and flexible generation of analog arrays

Special Layout Techniques for Analog IC Design

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