SVA: The Power of Assertions in SystemVerilog

Cerny, Eduard; Dudani, Surrendra; Havlicek, John; Korchemny, Dmitry

doi:10.1007/978-3-319-07139-8

Cited by 15 publications

(4 citation statements)

References 33 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…One of the critical points of the VPU is the interface, so we decided to run down the OVI specifications and write System Verilog Assertions (SVA) [5] that check that it is behaving as expected, implementing more than 50. At the early stages of the UVM testbench development, they helped to identify bugs in the VPU, as well as problems in the UVM stimulation.…”

Section: F Assertionsmentioning

confidence: 99%

Functional Verification of a RISC-V Vector Accelerator

et al. 2023

View full text Add to dashboard Cite

We present the functional verification efforts for an academic RISC-V based vector accelerator, successfully taped-out in the context of the European Processor Initiative. For our novel RISC-V based decoupled vector accelerator, we built a verification infrastructure consisting of a UVM environment, performing step by step co-simulation of all vector instructions, using the Spike instruction set simulator as a reference model. Furthermore, for validating this complex design connected to a scalar core using a custom interface, we provided automated constrainedrandom test generation, simulation and error reporting, and CI/CD infrastructure. We found 3005 errors during this process and reached 95.79% functional coverage.

show abstract

Section: F Assertionsmentioning

confidence: 99%

Functional Verification of a RISC-V Vector Accelerator

et al. 2023

View full text Add to dashboard Cite

show abstract

“…Eisner et al [13,14] have developed LTL @ , which adds a clock operator to LTL to deal with time granularities in hardware systems. This is included in the international standards Property Specification Language (PSL, IEEE Standard 1850 [24]) [12] and SystemVerilog Assertions (SVA, in IEEE Standard 1800 [26]) [5]. The clock operator adds succinctness but not expressiveness and is its own dual.…”

Section: Jones Et Al Observe Inmentioning

confidence: 99%

An Application of Temporal Projection to Interleaving Concurrency

Moszkowski

Guelev

2015

Dependable Software Engineering: Theories, Tools, and Applications

View full text Add to dashboard Cite

We revisit the earliest temporal projection operator Π in discrete-time Propositional Interval Temporal Logic (PITL) and use it to formalise interleaving concurrency. The logical properties of Π as a normal modality and a way to eliminate it in both PITL and conventional point-based Linear-Time Temporal Logic (LTL), which can be viewed as a PITL subset, are examined. We also formalise concurrency without Π, and relate the two approaches. Furthermore, Π and another standard PITL projection operator are interdefinable and both suitable for reasoning about different time granularities. We mention other (mostly interval-based) temporal logics with similar forms of projection, as well as some related applications and international standards.

show abstract

“…Formal verification is based on strict mathematical expressions and models [3] , which can describe the properties of design functions according to design specifications, analyze and prove them automatically, and give counterexamples if the proof fails. Formal verification was first adopted by EDA (Electronic Design Automation) tools, which can be traced back to the 1990s, and was applied to LEC (logic equivalence check) equivalence checking of RTL code and gate level code.…”

Section: Introductionmentioning

confidence: 99%

Formal verification in chip verification and study on its application practice

Shao

Yan

2023

Second International Conference on Algorithms, Microchips, and Network Applications (AMNA 2023)

View full text Add to dashboard Cite

With the development of integrated circuit industry, the complexity of integrated circuit chip design is becoming higher and higher, and the difficulty of verification is increasing exponentially. Verifying that the RTL description is as expected has become an increasingly important part of the modern integrated circuit industry. Compared with the traditional dynamic simulation verification, formal verification belongs to static verification, and it does not need manual inputting excitation, and can achieve the advantages of 100% coverage. This paper mainly introduces the status of formal verification, what formal verification is, the prospect of formal verification in the future, and provides a formal verification tool (VC Formal DPV) application practice model and several practical methods to significantly optimize its performance by taking the divider as an example.

show abstract

SVA: The Power of Assertions in SystemVerilog

Cited by 15 publications

References 33 publications

Functional Verification of a RISC-V Vector Accelerator

Functional Verification of a RISC-V Vector Accelerator

An Application of Temporal Projection to Interleaving Concurrency

Formal verification in chip verification and study on its application practice

Contact Info

Product

Resources

About