Susceptibility of Dual-Slope ADCs to Electromagnetic Interference: An Experimental Analysis

Quílez, Marcos; Casas, Óscar; Pallás-Areny, R.

doi:10.1109/imtc.2007.379398

Cited by 9 publications

(4 citation statements)

References 2 publications

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“…[3][4][5] According to different requirements, diverse A/D converters are applied to various occasions. [12][13][14] The theoretical memristor was put forward by Chua. [12][13][14] The theoretical memristor was put forward by Chua.…”

Section: Introductionmentioning

confidence: 99%

“…[6][7][8][9] Complementary metal-oxide-semiconductor (CMOS) dual-slope A/D converter is a high-resolution A/D converter, 10,11 which has good anti-interference and robustness performances. [12][13][14] The theoretical memristor was put forward by Chua. 15 Memristor not only has nonvolatility to keep memristance unchanged 16,17 but also has adjustable property that the voltage on memristor can change the memristance as well.…”

Section: Introductionmentioning

confidence: 99%

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A memristive dual‐slope A/D converter

Yang

Zeng

et al. 2019

Circuit Theory & Apps

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As an emerging device, memristor has several excellent properties like changeable memristance, nonvolatility, and nanoscale. Based on complementary metal-oxide-semiconductor (CMOS) dual-slope analog-to-digital (A/D) converter, this paper proposes a memristive dual-slope A/D converter. Owing to the usage of memristor, the proposed memristive A/D converter not only has more compact circuit structure and simpler control timing than the CMOS one but also has advantages over the existing memristive conversion circuits in circuit design and application. For the memristive A/D converter, a conversion process consists of two count procedures. By means of controlling the memristance change in the two count procedures, the A/D converter converts an analog signal to the corresponding digital count value. Meanwhile, the conversion result is inferred according to the circuit structure of the A/D converter. Then, combining the conversion process and PSPICE simulation, this paper analyzes the anti-interference performance of the A/D converter. Further, the robustness of the A/D converter is presented, applying the similar analysis methods. The analysis results demonstrate that the proposed A/D converter has good anti-interference and robustness performances.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A memristive dual‐slope A/D converter

Yang

Zeng

et al. 2019

Circuit Theory & Apps

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“…The use of such RDCs in presence of electromagnetic interference may lead to intolerable levels of error in their output. For schemes such as the DSRDC [9] the error due to interference can be reduced by choosing the integration period as a multiple of the time period of the expected interference frequency (50/60 Hz) [21]. However, as the de‐integration period of the scheme depends on the current value of the measurand, the error due to interference is still present, albeit, lower in magnitude.…”

Section: Introductionmentioning

confidence: 99%

Resistance‐to‐digital converter designed for high power‐line interference rejection capability

Gupta

George

2017

IET Circuits, Devices & Systems

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A novel resistance-to-digital converter (RDC), based on the integrating type analogue-to-digital converter principle, is presented in this study. The conversion time of the proposed scheme is not a function of the current value of the parameter being measured. Thus, by suitably setting this parameter, the converter can be made to reject the effects of interference at a particular frequency, such as, that due to power-line at 50/60 Hz. Error analysis was conducted to ascertain the effects of nonidealities of various components of the circuit, on its output. Simulation studies were carried out in LTSPICE to verify the linearity and the interference rejection capability of the converter. Further, a prototype RDC was developed in the laboratory and tested to confirm the results of the simulation.

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“…Among the existing types, the CDCs based on dual-slope (DS) conversion technique have the best power line/interference rejection, but they are limited by the fact that the integration period alone can be set as multiple of the time period of the interfering frequency f n , as the duration of the de-integration period (DIP) depends on the value of C x [2,3]. The CDC reported in [2] is based on the DS technique.…”

mentioning

confidence: 99%

Capacitance‐to‐digital converter for leaky capacitive sensors

Vooka

George

2016

Electron. lett.

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A novel capacitance-to-digital converter (CDC) that performs an accurate measurement of the capacitance of a leaky capacitive sensor is presented. The conversion technique of this CDC is novel, which helps to achieve the highest interference rejection compared with the exiting CDC topologies. The digital output from the CDC is directly proportional to the sensor capacitance, C x. It provides an accurate output even in the presence of a parasitic leakage resistance, R p , parallel to the sensor. A prototype CDC has been developed and tested. Worst-case error was found to be 0.1%. The CDC employs a sinusoidal excitation for the sensor, and is suitable for a variety of applications such as proximity or touch detection, detection of ice, level sensing, humidity measurement, etc. This CDC is well suited for applications where the conventional schemes fail to work due to the extreme interference from other sources, e.g. power line.

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Susceptibility of Dual-Slope ADCs to Electromagnetic Interference: An Experimental Analysis

Cited by 9 publications

References 2 publications

A memristive dual‐slope A/D converter

A memristive dual‐slope A/D converter

Resistance‐to‐digital converter designed for high power‐line interference rejection capability

Capacitance‐to‐digital converter for leaky capacitive sensors

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