Survey on FPGA Architecture and Recent Applications

Gandhare, Shubham; Karthikeyan, B.

doi:10.1109/vitecon.2019.8899550

Cited by 31 publications

(12 citation statements)

References 10 publications

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“…Therefore, in this analysis, an FPGA with a reconfiguration is used to implement two controllers -vector power, and frequency -voltage control (f/Hz). This configuration shows that a stable and potentially noise-reduction transition between controls can be achieved Gandhare et al [2019]; Shimoda et al [2019]. The main contribution of the present work is, 1.…”

Section: Introductionmentioning

confidence: 70%

FPGA Based Dual Controller Design for EMI Reduction in Dc-Dc Converters

Britto¹,

Saravanan²,

Kumar³

et al. 2021

Proceedings of the First International Conference on Computing, Communication and Control System, I3CAC 2021, 7-8 June 2021, Bh

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In high frequency electronic power converters, the suppression of Electromagnetic Interference (EMI) and the improvement of Electromagnetic Compatibility (EMC) have become important. Field Programmable Logic Array (FPGA) has become a low-cost platform offering the ability for power electronics to create unique EMC control techniques. In FPGA, however, it is complicated to accomplish some of the features required in the power electronic control system. The key difficulties are related to the operation of the fixed point, and the need to change the dynamic number range. Constructing filters to comply with the EMI limits is a significant part of the production cost of power converters. Therefore, a simple yet powerful dual controller based FPGA is therefore discussed to provide a substantial motor control for noise reduction. A model of a prototype has been tested and hardware findings indicate a substantial drives with low performance requirements. In terms of speed and torque, the theoretical algorithms, hardware information and experimental findings are presented and discussed.

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Section: Introductionmentioning

confidence: 70%

FPGA Based Dual Controller Design for EMI Reduction in Dc-Dc Converters

Britto¹,

Saravanan²,

Kumar³

et al. 2021

Proceedings of the First International Conference on Computing, Communication and Control System, I3CAC 2021, 7-8 June 2021, Bh

View full text Add to dashboard Cite

show abstract

“…It is the base for prototyping and further modifications. The architecture can be either unique or selected from a variety of existing solutions that differ in the structure of routing resources [13,14] (island style and hierarchical FPGA architectures), the structure of a logic element (LE) and a logic array blocks (LABs) (LE in FPGAs by Altera [15], a configuration logic block in FPGAs by Xilinx [16], a versatile logic cell in FPGAs by Microsemi [17]). The final circuit architecture from all the variety available can be selected using physical constraints such as the package size or the chip area required to fit the configuration memory.…”

Section: Software Circuit Prototyping Methodsmentioning

confidence: 99%

“…Let us denote by a logical function defined on the Cartesian product taking value 1 if and only if s is actually used in : (14) i.e., or…”

mentioning

confidence: 99%

Designing FPGAs and Reconfigurable SoCs Using Methods of Program Analysis and Prototyping

et al. 2021

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This paper describes approaches and methods for software circuit prototyping of field-programmable gate arrays (FPGAs) and reconfigurable systems-on-a-chip (RSoC). Software circuit prototyping is a new stage in the design flow for FPGAs and reconfigurable SoCs in contrast to the classical FPGA-based prototyping using ready-made FPGA chips. It allows to evaluate the efficiency of the user circuit design implementation and select the basic chip architecture before its tape-out because of the computer-aided design (CAD) tools promptly adapting to any changes in the structure, circuitry and layout of a basic chip. The flexible and dynamic software customization to maintain the required FPGA or RSoC architecture is provided by the developed formalized description of the basic circuit, which is used in CAD and is represented in this paper. This formalized description can be used both for the analysis of the basic chip and for the analysis of a user circuit design implemented on an FPGA or RSoC.

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“…An FPGA contains a great many logic, arithmetic, and memory elements, which users can configure to implement custom circuits. Thus far, many works have designed an FPGA as an accelerator, used in various fields [32]. However, an FPGA first needs to function as an NIC to be an accelerator for a software data plane.…”

Section: Evaluating Fsnic As Acceleratormentioning

confidence: 99%

AccelSDP: A Reconfigurable Accelerator for Software Data Plane Based on FPGA SmartNIC

et al. 2021

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Software-defined networking (SDN) has attracted much attention since it was proposed. The architecture of the SDN data plane is also evolving. To support the flexibility of the data plane, the software implementation approach is adopted. The software data plane of SDN is commonly implemented on a commercial off-the-shelf (COTS) server, executing an entire processing logic on a commodity CPU. With sharp increases in network capacity, CPU-based packet processing is overwhelmed. However, completely implementing the data plane on hardware weakens the flexibility. Therefore, hybrid implementation where a hardware device is adopted as the accelerator is proposed to balance the performance and flexibility. We propose an FPGA SmartNIC-based reconfigurable accelerator to offload some of the operation-intensive packet processing functions from the software data plane to reconfigurable hardware, thus improving the overall data plane performance while retaining flexibility. The accelerated software data plane has a powerful line-rate packet processing capability and flexible programmability at 100 Gbps and higher throughput. We offloaded a cached-rule table to the proposed accelerator and tested its performance with 100 GbE traffic. Compared with the software implementation, the evaluation result shows that the throughput can achieve a 600% improvement when processing small packets and a 100% increase in large packet processing, and the latency can be reduced by about 20× and 100×, respectively, when processing small packets and large packets.

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Survey on FPGA Architecture and Recent Applications

Cited by 31 publications

References 10 publications

FPGA Based Dual Controller Design for EMI Reduction in Dc-Dc Converters

FPGA Based Dual Controller Design for EMI Reduction in Dc-Dc Converters

Designing FPGAs and Reconfigurable SoCs Using Methods of Program Analysis and Prototyping

AccelSDP: A Reconfigurable Accelerator for Software Data Plane Based on FPGA SmartNIC

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