Survey of branch prediction schemes for pipelined processors

Thangarajan, K.; Mahmoud, Wagdy; Ososanya, Esther; Balaji, Pavan

doi:10.1109/ssst.2002.1027060

Cited by 8 publications

(7 citation statements)

References 11 publications

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“…The small application code associated with network applications results in predictor saturation above 1024 entries, significantly below the 16K-entries found in [12] to be required for general purpose processing. However there remains a sizable performance difference between HPA and PPA tasks, with a similar predictor providing almost 7% less correct predictions when executing RADIX (88.9%) routing compared to any PPA task (>95.8%).…”

Section: A Branch Pattern History Table Sizementioning

confidence: 88%

“…Following a similar architecture to the ARM 9TDMI processor, the transistor cost of the PE can be estimated at 111,000 [12]. Assuming additional registers are needed for context switching, data transfer, etc, we can determine the cost of a single 'shared-master' 16 * 32-bit register bank as 32 + (16 *32) latches, or ~6500 transistors per bank.…”

Section: Appendixmentioning

confidence: 99%

“…With 2-bit up/down saturating counter requiring 28 transistors to implement, a 2KB (or 8K-entry) would require over 229,000 transistors to implement. The 2-KB bimodal examined in [12] is therefore too expensive to implement next to a simple RISC PE, while more complex predictors such as a 2-level predictor or combining predictor would occupy significantly more area than the processor. When examining branch predictor performance on network processor architectures, the fundamental question is not whether performance increases can be extracted from such solutions, but if such predictors are justified relative to the small footprint of the PE.…”

Section: Appendixmentioning

confidence: 99%

“…However, when compared to the small cache-less area cost of a PE these three solutions require a large amount of transistors to implement. Further information on branch prediction schemes can be found in [11,12].…”

Section: Introductionmentioning

confidence: 99%

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Branch prediction for network processors

Bermingham¹,

Liu²,

Wang³

et al. 2008

2008 International Conference on Microelectronics

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Abstract-Meeting the future requirements of higher bandwidth while providing ever more complex functions, future network processors will require a number of methods of improving processing performance. One such method will involve deeper processor pipelines to obtain higher operating frequencies. Mitigation of the penalty costs associated with deeper pipelines have achieved by implementing prediction schemes, with previous execution history used to determine future decisions. In this paper we present an analysis of common branch prediction schemes when applied to network applications. Using widespread network applications, we find that unlike general purpose processing, hit rates in excess of 95% can be obtained in a network processor using a small 256-entry single level predictor. While our research demonstrates the low silicon cost of implementing a branch predictor, the long run times of network applications can leave the majority of the predictor logic idle, increasing static power and reducing device utilization.

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Section: A Branch Pattern History Table Sizementioning

confidence: 88%

Section: Appendixmentioning

confidence: 99%

Section: Appendixmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Branch prediction for network processors

Bermingham¹,

Liu²,

Wang³

et al. 2008

2008 International Conference on Microelectronics

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“…Dynamic branch prediction, such as branch target buffers(BTB), pattern history table (PHT), branch target address cache (BTAC), uses information gathered during the run-time of the program to predict branch direction [4]. For the variable bytecode length, we modified BTB and make the new prediction unit to match the character of bytecode.…”

Section: Branch Predictionmentioning

confidence: 99%

Accelerating java for ubiquitous devices

Lü

Zheng

The Fourth International Conference onComputer and Information Technology, 2004. CIT '04.

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Nowadays, Java has become the most popular and portable language for its "write once, run anywhere" promise, which makes it ideal for developing applications for ubiquitous devices. While the Java technology comes with compromises as well: the platform-independence is achieved via various JVMs, which are platform-specific; the execution speed of Java bytecode in JVMs is not as fast as native code written in C/C++. In this paper, we present a portable JVM and an asynchronous Java accelerator for ubiquitous devices. The JVM strives to be as crossplatform as possible by defining clear application programming interfaces between different modules and the Java accelerator was specially designed for accelerating execution of Java bytecode with low power consumption, which is critical to ubiquitous devices.

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Implementation and comparison of bi-modal dynamic branch prediction with static branch prediction schemes

Nain

Chaudhary

2021

Int. j. inf. tecnol.

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Survey of branch prediction schemes for pipelined processors

Cited by 8 publications

References 11 publications

Branch prediction for network processors

Branch prediction for network processors

Accelerating java for ubiquitous devices

Implementation and comparison of bi-modal dynamic branch prediction with static branch prediction schemes

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