Surface charge control during high-current ion implantation: characterization with CHARM-2 sensors

Abstract

DISCLAIMERPortions of this document may be illegible in electronic image products. Images are produced from the best available original document.IIT/94, Catania, Italy, June [13][14][15][16][17] Rev 4.0Thu., Aug. 18, 1994 . AbstxactStudies of the charging effects during implantation with 9200 and 9500 tools using EEPROM-based sensors, CHARM-2, are,reported for 6OkeV As beams. . htroductionThe thinning of gate oxides for advanced MOS devices has increased the sensitivity of these oxides to excessive charge flows and potentials during exposure to ion beam processing. Tracking the intrinsic breakdown voltage of S i 0 2 as =lOMV/cm, this corresponds to a +1OV limit for gate-to-substrate potentials for lOOA oxides (Fig. 1). This sensitivity is further tightened by concern for pre-breakdown damage (generated by current flows at potentials greater than 40% of breakdown conditions) as well as charge sharing and current funneling effects of long-line gateinterconnect structures [1,2]. The reduction of intrinsic breakdown voltage has driven the development of supplemental electron sources with ever-decreasing electron energies and increased coupling to the ion beam plasma (Fig.1).Additional progress towards charge control has been limited by the lack of detailed understanding of the interact-ion of the ion beam plasma with device structures on the wafer surface [3,4]. If the ion beam is interpreted as a plasma of some complexity [5], a variety of charged species must be considered (Fig. 2). In addition t o the energetic dopant ions, the ion beam plasma contains a significant number of ''slow ions", created by collisions between the energetic dopant ions and The electron population is essentially equal t o the density of the total ion species in the regions of the beamline where the absence of acceleration fields allow for quasi-neutrality of the beam plasma. The electron energy spectra is however quite complex. Those electrons which are trapped in the ion beam column have energies of the order of the beam potential while the-energies of electrons which enter the ion beam plasma from a wafer charge control system are determined by the local potentials in the charge control device [3]. Test Structures for Surface Potential and Charge Flows: CHARM-2Device-scale sensors using EEPROM-based structures (Fig-3) f o r measurement of surface potentials.and net charge flows provide a new and detailed view of plasma conditions on the wafer surface during implantation. CHARM-2 (CHARge Monitor) devices [S-111 use large-area Al electrodes tied to the control gate of an EEPROM transistor to sense the local surface potential. Electrodes which are tied to the Si substrate through poly-Si resistors measure the net charge flux on the electrode. Voltages and currents on the wafer surface are inferred from shifts in the transistor threshold voltage after exposure to an ion beam process environment. , Many of the charge collection electrodes are connected to the Si wafer substrate through poly resistors. Low-resistance shunts are used for s...

Ion beams in silicon processing and characterization

“…55 is a map of the surface potential variation over a wafer exposed to a ''native'' 16 mA As ion beam with no charge control techniques in operation. 169 The high surface potentials (Ϸ17 V) seen near the edges of the wafer where the ion beam enters and leaves the wafer surface are reduced in the middle portion of the wafer to Ϸ10 V by the effects of secondary electrons from the Al sensor pads. Analysis of the flux-voltage characteristics of the ion beam plasma shows that the lowering of surface potentials in the center portions of the wafer was accompanied by an increase in the plasma density over the wafer surface to Ϸ100ϫ the ion beam density.…”

“…169,170 Additional charge flows that can play a role are ͑1͒ charged atoms that evolve from the outgassing of materials from photoresist layers, ͑2͒ secondary ions generated on surface structures, and ͑3͒ unusual conduction paths on the wafer surface, such as surface layers of ion bombarded oxides.…”