Suppression of metal contamination by gettering

Teo, J.W.Y.; Lim, Han Woong; Yu, Jin; Huang, Jian; Chew, W.C.; Leong, Chee Kong; Gn, Fang Hong; Li, M.F.; Su, Guowei

doi:10.1109/ipfa.2001.941489

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat

DOI: 10.1109/ipfa.2001.941489

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Suppression of metal contamination by gettering

J.W.Y. Teo¹,

Han Woong Lim²,

Jin Yu³

et al.

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“…A previous work has demonstrated that manufacturing tools cause contaminations with such heavy metals as Al, Zn, Ni, Cu, and Fe at a concentration of the order of 10 12 -10 14 atoms/cm 2 . 9 Meanwhile, to study the effects of these contaminants in the subsequent wet cleaning process, the cleaning of contaminated wafers in various chemical baths, such as buffered oxide etch, diluted HF, H 2 O 2 and SC-1 ͑NH 4 OH + H 2 O 2 + H 2 O͒ must be examined. Additionally, the levels of contamination of the bath chemicals and the surfaces of the processed wafers must be measured using various analytical approaches.…”

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Characteristics of Spontaneous Reaction Occurred by Metal Contamination and Silicon Substrate for Ultralarge-Scale Integration Semiconductor Process

Chen

2008

J. Electrochem. Soc.

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Heavy metals such as Cu, Fe, and Ni are well known to cause defects in Si substrate and to degrade thin oxide quality in ultralarge-scale integration ͑ULSI͒ circuits. This degradation can seriously reduce yield and long-term reliability, which are the two critical factors in ULSI manufacturing. Metallic contamination originates in such process materials as gases and wet chemicals. As devices shrink, microcontamination is having an increasingly negative effect on operation function and yield. Semiconductor manufacturers can markedly increase wafer yield by reducing contamination. This work analyzes the contamination of processed wafers by heavy metals before the deposition of gate oxide. Many bamboo-shoot-like defects are present on the wafer edge. Additionally, many pits are also formed in the active region of a device when silicon substrate suffers from heavy metallic contamination. Transmission electron microscopy ͑TEM͒ and energy dispersive spectroscopy ͑EDS͒ are adopted to study the bamboo-shoot-like defects and pit defects. A possible mechanism was identified to explain the problem stage in manufacturing process. This work demonstrates the spontaneous dissolution of the contaminating metal in the silicon substrate. Tiny pits are becoming a serious problem in the manufacturing of submicrometer and deep-submicrometer ULSIs ͑Ͻ0.13 m͒, which always suffer from yield loss at the wafer edge because of bamboo-shoot-like defects that are associated with design rule limitations. A detailed analysis and process flow check reveal that metal contamination generates tiny pits around the wafer edge in the raw material wafer process flow. These tiny pits result in bamboo-shoot-like defects in the non-o.d. ͑periphery͒ region and 0.02 m pits in the o.d. ͑active͒ region. These two defects cause failure of the device because of leakage. This work is the first to describe this issue regarding ULSI manufacturing and demonstrates that tiny pits represent high risk of device operation at the deep submicron level. An effective solution is to more strictly limit the degree of metallic contamination.Contamination of wafers during manufacturing by such metals as Al, Fe, Cr, W, and Ta, for example, may lower the device yield. These metals are commonly adopted in the fabrication of semiconductors and can be transported to the wafer by a sputtering, beam constituents, or chemical process. Contamination issues in the microelectronic industry continue to play a crucial role in attaining the industry's roadmap goals. For the submicron technology nodes, along with metals and other particles, organic compounds are suspected to be critical contaminants.Previous works 1 have demonstrated that even though today's process chemicals are quite pure, they may be easily contaminated with metal ions because of poor handling or storage techniques. Such metal impurities, if deposited on the wafer surface during processing, can generate generation-recombination centers in silicon, increasing reverse-bias junction leakage by dislocation decoration and sta...

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Characteristics of Spontaneous Reaction Occurred by Metal Contamination and Silicon Substrate for Ultralarge-Scale Integration Semiconductor Process

Chen

2008

J. Electrochem. Soc.

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Suppression of metal contamination by gettering

Cited by 1 publication

References 5 publications

Characteristics of Spontaneous Reaction Occurred by Metal Contamination and Silicon Substrate for Ultralarge-Scale Integration Semiconductor Process

Characteristics of Spontaneous Reaction Occurred by Metal Contamination and Silicon Substrate for Ultralarge-Scale Integration Semiconductor Process

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