Supporting fault tolerance in an industrial environment: the AMATISTA approach

Gonazlez, I.; Berrojo, L.

doi:10.1109/olt.2001.937839

Cited by 13 publications

(6 citation statements)

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“…This paper is focused on the behavioural effects produced by Single Event Upsets (SEU). The most commonly used fault model for SEU effects is the bit-flip, which affect circuit memory elements [16].…”

Section: Transient Fault Emulationmentioning

confidence: 99%

Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation

López-Ongil

García-Valderas

Portela-García

et al. 2007

IEEE Trans. Nucl. Sci.

119

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The appearance of nanometer technologies has produced a significant increase of integrated circuit sensitivity to radiation, making the occurrence of soft errors much more frequent, not only in applications working in harsh environments, like aerospace circuits, but also for applications working at the earth surface. Therefore, hardened circuits are currently demanded in many applications where fault tolerance was not a concern in the very near past. To this purpose, efficient hardness evaluation solutions are required to deal with the increasing size and complexity of modern VLSI circuits. In this paper, a very fast and cost effective solution for SEU sensitivity evaluation is presented. The proposed approach uses FPGA emulation in an autonomous manner to fully exploit the FPGA emulation speed. Three different techniques to implement it are proposed and analyzed. Experimental results show that the proposed Autonomous Emulation approach can reach execution rates higher than one million faults per second, providing a performance improvement of two orders of magnitude with respect to previous approaches. These rates give way to consider very large fault injection campaigns that were not possible in the past.

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Section: Transient Fault Emulationmentioning

confidence: 99%

Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation

López-Ongil

García-Valderas

Portela-García

et al. 2007

IEEE Trans. Nucl. Sci.

119

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“…According to requirements coming from some European space and car industries [14], the fault model we consider is the (single/multiple) bit-flip in the circuit storage elements, since it closely matches SEU effects. As pointed out in [14], SEUs are the major source of concerns; therefore, in this paper we do not consider more complex effects, such as single-event transients.…”

Section: A Background and Assumptionsmentioning

confidence: 99%

“…As pointed out in [14], SEUs are the major source of concerns; therefore, in this paper we do not consider more complex effects, such as single-event transients.…”

Section: A Background and Assumptionsmentioning

confidence: 99%

Exploiting circuit emulation for fast hardness evaluation

Civera

Macchiarulo

Rebaudengo

et al. 2001

IEEE Trans. Nucl. Sci.

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“…This current ( ) and your collected charge are modeled in (1a) and (1b): where 0 is the current generated by the charges, is the time constant for initially establishing the ion track and is the collection time constant of the junction [1], [4]. Programs such as AMATISTA [5] are used in the industrial area to develop fault-tolerant circuits. Another software, a FPGA-based fault simulator [6] use partial reconfiguration to simulate SEU faults by changing the interconnections in FPGAs.…”

Section: Introductionmentioning

confidence: 99%

SET and SEU simulation toolkit for LabVIEW

Bartra

Reis

2011

2011 12th European Conference on Radiation and Its Effects on Components and Systems

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Nowadays, the fault simulation is an important step in any IC design. Predicting the behavioral faults of any process step is essential to ensure that the design is well implemented. During the simulation various problems can be detected and corrected. It is presented a tool to simulate the effects that occur when a source of fault is inserted in a digital circuit, especially SEU faults. To model a fault, it was also developed a TMR method capable of verifying the existence of a fault and to not let it spread through the whole circuit. It was also developed a Voltage Controlled Oscillator (VCO) to view fault effects in analog circuits. LabVIEW tool is used to create a set of virtual instruments to simulate SEUs. It is efficient in modeling the Characteristics of SETs. It is possible with this toolkit to replicate the effects of SEUs and SETs described in the literature.

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Supporting fault tolerance in an industrial environment: the AMATISTA approach

Cited by 13 publications

References 0 publications

Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation

Autonomous Fault Emulation: A New FPGA-Based Acceleration System for Hardness Evaluation

Exploiting circuit emulation for fast hardness evaluation

SET and SEU simulation toolkit for LabVIEW

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