Supporting early development of advanced high-performance logic with synchrotron orbital radiation lithography: a feasibility evaluation

Abstract

The Synchrotron Xray Lithography (XRL) project described in this paper was conducted as a learning and feasibility vehicle for gate level lithography in support of IBM's most advanced CMOS logic programs. An electrically probeable multilevel lithography test site was developed and characterized to exercise critical design, mask manufacture, alignment, exposure, and metrology issues in the 150-350nm line width range. Masks built with an elaborate dual mask-writer process involving an EL3+ shaped beam 50kV electron beam mask making tool in the IBM Burlington Advanced Mask Facility (AMF) and a VS-5 100kV thermal field emission vector scan electron beam lithography tool at the IBM Watson Research Center yielded lSOnm resolution and very good image size control at 200nm line widths. A fully capped silicided polysilicon gate stack was chosen for the electrical measurements in order to develop and demonstrate the XRL and related reactive ion etch (RIE) process on a realistic, product-like substrate. This paper addresses test site design issues, elaborates on the mask manufacturing process, and presents SEM and electrical data from wafers processed at IBM's Advanced Semiconductor Technology Center (ASTC). The data presented demonstrate the feasibility of supporting early device development and process integration with XRL and highlight the need for high resolution, defect free, proximity corrected masks to fully exploit the capabilities of Xray Lithography.

Sub-0.2 micron gate lithography using E-beam, X-ray and optical technologies-an overview

“…Geometries in the 0.15 um range have been produced by IBM [5] , Toshiba [6] and others. X-ray lithography has excellent throughput potential [7] with results in the 30-60 wph range and a goal of 100-200 wph.…”