Supporting Bulk Synchronous Parallelism with a high‐bandwidth optical interconnect

Abstract

SUMMARYThe list of applications requiring high-performance computing resources is constantly growing. The cost of inter-processor communication is critical in determining the performance of massively parallel computing systems for many of these applications. This paper considers the feasibility of a commodity processorbased system which uses a free-space optical interconnect. A novel architecture, based on this technology, is presented. Analytical and simulation results based on an implementation of BSP (Bulk Synchronous Parallelism) are presented, indicating that a significant performance enhancement, over architectures using conventional interconnect technology, is possible.

Design and construction of the high-speed optoelectronic memory system demonstrator

“…Early examples of possible architectures may be found in Refs. [18,19], for example. The HOLMS package takes such architectures out of the theoretical computer science realm.…”

Architecture and tolerancing for a matrix operation on the optical highway

“…In it, 3,4 processors or commodity PCs are connected together optically. Smart pixels are used as a glue layer between the processors and the optical highway.…”

Optimization of reconfigurable optically interconnected systems for parallel computing

“…It is therefore beneficial to reduce this routing latency by using the optics to reduce the number of routing stages in the network by exploiting the large distance scalability available, even if the bandwidth must be reduced to account for the larger losses. Such a system is presented in [3] in which the speed of operation of a single optical line is reduced over long distances but the number of lines utilized is increased, resulting in the same aggregate bandwidth but at a reduced routing latency due to fewer steps.…”