Support Tool for the Combined Software/Hardware Design of On-Chip ELM Training for SLFF Neural Networks

Bataller-Mompeán, Manuel; Martínez-Villena, José M.; Muñoz, Andrés Pedreño; Francés-Víllora, Jose V.; Guerrero, Juan; Węgrzyn, Marek; Adamski, Marian

doi:10.1109/tii.2016.2554521

Cited by 11 publications

(7 citation statements)

References 18 publications

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“…Due to the efficient learning rate, the ELM algorithm is gaining popularity in the hardware implementations which require frequent on-chip training [49]- [51]. Therefore, the proposed Enhanced MW RSSA-ELM algorithm is suitable to implement in surgical hand-held tools, such as Micron and its descendant ITrem, for cancellation of tremor in realtime.…”

Section: Discussionmentioning

confidence: 99%

Physiological Tremor Filtering Without Phase Distortion for Robotic Microsurgery

Adhikari

Tatinati

Veluvolu

et al. 2022

IEEE Trans. Automat. Sci. Eng.

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All existing physiological tremor filtering algorithms, developed for robotic microsurgery, use non-linear phase pre-filters to isolate the tremor signal. Such filters cause phase distortion to the filtered tremor signal and limit the filtering accuracy. We revisited this long-standing problem to enable filtering of the physiological tremor without any phase distortion. We developed a combined estimation-prediction paradigm that offers zero-phase type filtering. The estimation is achieved with the mathematically modified recursive singular spectrum analysis algorithm and the prediction is delivered with the standard extreme learning machine. In addition, to limit the computational cost; we developed two moving window versions of this structure, appropriate for real-time implementation. The proposed paradigm preserved the natural phase of the filtered tremor. It achieved the key performance index of error limitation below 10µm, yielding the estimation accuracy larger than 70%, at a time delay of 36ms only. Both moving window versions of the proposed approach restricted the computational cost considerably; whilst offering the same performance. It is for the first time that effective estimation of the physiological tremor is achieved, without any pre-filtering and phase distortion. This proposed method is feasible for real-time implantation. Clinical translation of the proposed paradigm can significantly enhance the outcome in hand-held surgical robotics. Note to Practitioners-The imprecision caused by physiological hand tremor in microsurgeries has motivated researchers to innovate an efficient tremor compensating technique that can improve the surgical performance. Yet, all the existing tremor filtering algorithms, implemented in hand-held surgical instruments, use non-linear phase pre-filters to separate the tremor signal. The inherent phase distortion caused by such pre-filters restricts the filtering performance significantly and renders the existing methods inadequate for hand-held robotic surgery. Motivated by this, we proposed a novel estimator-predictor based framework, by adopting the modified recursive singular spectrum analysis estimator and the extreme learning machine predictor. The proposed framework filters the tremor signal accurately, without distorting it, but at a small fixed lag. In a set of rigorous testing performed by emulating a real-time processing, the proposed Manuscript received August 29, 2019.

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Section: Discussionmentioning

confidence: 99%

Physiological Tremor Filtering Without Phase Distortion for Robotic Microsurgery

Adhikari

Tatinati

Veluvolu

et al. 2022

IEEE Trans. Automat. Sci. Eng.

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“…However, in existing computer vision-based classification methods, solutions often have limited performance capabilities and fail to offer an integrated embedded hardware/software paradigm that can produce output in a digital format with real-time continuous update capabilities. This paper addresses this technological gap by offering a hardware/software-based co-design that could help overcome some of the limitations of existing AI-enabled classifiers by extracting kidney cell microscopic images and testing the classifier in real time on a reconfigurable FPGA device [1][2][3][4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Computer Vision-Based Kidney’s (HK-2) Damaged Cells Classification with Reconfigurable Hardware Accelerator (FPGA)

et al. 2022

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In medical and health sciences, the detection of cell injury plays an important role in diagnosis, personal treatment and disease prevention. Despite recent advancements in tools and methods for image classification, it is challenging to classify cell images with higher precision and accuracy. Cell classification based on computer vision offers significant benefits in biomedicine and healthcare. There have been studies reported where cell classification techniques have been complemented by Artificial Intelligence-based classifiers such as Convolutional Neural Networks. These classifiers suffer from the drawback of the scale of computational resources required for training and hence do not offer real-time classification capabilities for an embedded system platform. Field Programmable Gate Arrays (FPGAs) offer the flexibility of hardware reconfiguration and have emerged as a viable platform for algorithm acceleration. Given that the logic resources and on-chip memory available on a single device are still limited, hardware/software co-design is proposed where image pre-processing and network training were performed in software, and trained architectures were mapped onto an FPGA device (Nexys4DDR) for real-time cell classification. This paper demonstrates that the embedded hardware-based cell classifier performs with almost 100% accuracy in detecting different types of damaged kidney cells.

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“…In order to assist to inexperienced users in the hardware implementation of neural networks, some works propose neural network software design tools using user-friendly visual graphical interfaces, where the hardware configuration files are automatically generated according to the user options. This is the case in [14], where a complete design environment for migrating neural networks from software to FPGA hardware, including network training, was described, or [15], which describes an end-user design environment where any FFNN can be modeled, simulated, and later programmed on an FPGA.…”

Section: Introductionmentioning

confidence: 99%

A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks

et al. 2019

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New chips for machine learning applications appear, they are tuned for a specific topology, being efficient by using highly parallel designs at the cost of high power or large complex devices. However, the computational demands of deep neural networks require flexible and efficient hardware architectures able to fit different applications, neural network types, number of inputs, outputs, layers, and units in each layer, making the migration from software to hardware easy. This paper describes novel hardware implementing any feedforward neural network (FFNN): multilayer perceptron, autoencoder, and logistic regression. The architecture admits an arbitrary input and output number, units in layers, and a number of layers. The hardware combines matrix algebra concepts with serial-parallel computation. It is based on a systolic ring of neural processing elements (NPE), only requiring as many NPEs as neuron units in the largest layer, no matter the number of layers. The use of resources grows linearly with the number of NPEs. This versatile architecture serves as an accelerator in real-time applications and its size does not affect the system clock frequency. Unlike most approaches, a single activation function block (AFB) for the whole FFNN is required. Performance, resource usage, and accuracy for several network topologies and activation functions are evaluated. The architecture reaches 550 MHz clock speed in a Virtex7 FPGA. The proposed implementation uses 18-bit fixed point achieving similar classification performance to a floating point approach. A reduced weight bit size does not affect the accuracy, allowing more weights in the same memory. Different FFNN for Iris and MNIST datasets were evaluated and, for a real-time application of abnormal cardiac detection, a ×256 acceleration was achieved. The proposed architecture can perform up to 1980 Giga operations per second (GOPS), implementing the multilayer FFNN of up to 3600 neurons per layer in a single chip. The architecture can be extended to bigger capacity devices or multi-chip by the simple NPE ring extension.INDEX TERMS Feedforward neural networks -FFNN, systolic hardware architecture, FPGA implementation, neural network acceleration, deep neural networks.

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Support Tool for the Combined Software/Hardware Design of On-Chip ELM Training for SLFF Neural Networks

Cited by 11 publications

References 18 publications

Physiological Tremor Filtering Without Phase Distortion for Robotic Microsurgery

Physiological Tremor Filtering Without Phase Distortion for Robotic Microsurgery

Computer Vision-Based Kidney’s (HK-2) Damaged Cells Classification with Reconfigurable Hardware Accelerator (FPGA)

A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks

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