Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS

Mesgarani, Ali; Alam, Mustafa N.; Nelson, Fan Z.; Ay, Suat U.

doi:10.1109/mwscas.2010.5548658

Cited by 62 publications

(20 citation statements)

References 9 publications

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“…However, these techniques result in increased circuit complexity, higher power consumption, degraded energy efficiency, or slower operation. In addressing some of these drawbacks, a new mixed-signal design technique called supply boosting (SBT) was proposed [13][14][15]. A new comparator topology has been developed using supply boosting resulting in low-voltage, and energy efficient operations.…”

Section: Open Accessmentioning

confidence: 99%

“…A modified version of the charge pump circuit design technique is proposed and called supply boosting technique (SBT) [13][14][15]. In supply boosted circuits, system supply voltage is boosted locally only once allowing boosted voltages such as clock and supply voltages to drop from their boosted level, V AAB , as shown in Figure 1b.…”

Section: Supply Boosting Technique (Sbt)mentioning

confidence: 99%

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Energy Efficient Supply Boosted Comparator Design

2011

JLPEA

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This paper presents a new mixed-signal design technique called supply boosting technique (SBT) and the design of an energy efficient, sub-1 V supply boosted comparator (SBC) in a standard complementary metal oxide semiconductor (CMOS) process. The selected CMOS process does not allow sub-1 V operation with a wide input range due to high threshold voltage (high-V TH ) of MOS transistors (+0.8 V/−0.9 V). Despite this, the proposed comparator operates sub-1 V supply voltages with input common mode voltage larger than 60% of supply voltage by utilizing a supply boosting technique. The measured power consumption of the supply boosted comparator for 1 V supply was 90 nW and speed was 6500 conversions per second, resulting in 14 pJ per conversion energy efficiency.

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Section: Open Accessmentioning

confidence: 99%

Section: Supply Boosting Technique (Sbt)mentioning

confidence: 99%

Energy Efficient Supply Boosted Comparator Design

2011

JLPEA

Self Cite

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“…Besides, low-voltage operation results in limited common-mode input range, which is important in many high-speed ADC architectures, such as flash ADCs. Many techniques, such as supply boosting methods [2], [3], techniques employing body-driven transistors [4], [5], current-mode design [6] and those using dual-oxide processes, which can handle higher supply voltages have been developed to meet the low-voltage design challenges. Boosting and bootstrapping are two techniques based on augmenting the supply, reference, or clock voltage to address input-range and switching problems.…”

Section: Introductionmentioning

confidence: 99%

High Speed and Low Power Double-Tail Comparator using Switching Transistor

Balla¹,

YKUNTAM²

2014

International Journal of Advanced Research in Computer and Comm

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Abstract:The high speed conversions are needed in the faster analog -to-digital converters. The accuracy of comparators is defined by its power consumption and speed. Many high speed ADCs, such as flash ADCs, require High speed, Low power comparators with small chip area. Conventional dynamic latched comparators suffer from low supply voltages especially when threshold voltage of the devices is not scaled at the same pace as the supply voltages of the modern CMOS process. The proposed comparator System has lower input-referred latch offset voltage and higher load drivability than the conventional dynamic latched comparators. In the dynamic Double tail comparator the simulation in a CMOS technology. In the Proposed dynamic Double tail comparator System both the power consumption and delay time will be significantly reduced. The maximum clock frequency of the proposed comparator can be reduced at modified supply voltages.

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“…But, all the above techniques require either large overhead for pre/postprocessing or long latency. Further many design issues like as speed, accuracy, design overhead, power consumption etc., should not be addressed for fast multiplication [8].…”

Section: Introduction Multiplication Is Of Immense Importance In Dmentioning

confidence: 99%

Implementation of reversible vedic multiplier for low latency and reduced resources utilization applications

Rao¹,

Rao²

2014

International Journal of Advanced Research in Computer and Comm

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Abstract:Reversible computation is an emerging area of research, having applications in nanotechnology, low power design and quantum computing. It is proved that reversible logic has zero internal power dissipation. Multiplication plays an important role in the processors. It is one of the basic arithmetic operations and it requires more hardware resources and processing time than the other arithmetic operations. Vedic mathematic is the ancient Indian system of mathematic. It has a unique technique of calculations based on 16 Sutras. The multiplication sutra between these 16 sutras is the Urdhva Tiryakbhyam sutra which means vertical and crosswise. In this paper it is used for designing a low latency and reduced resources 4*4 Vedic multiplier. The important parameters in designing reversible logic circuits like no of flipflops,no of LUT's , Total Equivalent gate count for design are estimated and reported for our proposed reversible Vedic multiplier.

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Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS

Cited by 62 publications

References 9 publications

Energy Efficient Supply Boosted Comparator Design

Energy Efficient Supply Boosted Comparator Design

High Speed and Low Power Double-Tail Comparator using Switching Transistor

Implementation of reversible vedic multiplier for low latency and reduced resources utilization applications

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